Breaking The Three Laws

 

Double performance with SLR to IO Bank to Connector 1 to 1 mapping for Xilinx UltraScale VU440

A long time ago in a blog since forgotten I talked about the importance of 1:1 mapping between the Xilinx FPGA Super Logic Region, SLR, to IO Bank to Connector. The result of which can be as much as 2X system performance thanks to efficient mapping of the design to the FPGA.

To recap, the Xilinx Virtex-7 2000T FPGA was made up of four(4) SLR’s and included fifty(50) IO’s per bank. The new Xilinx UltraScale VU440 is made up of three(3) SLR’s and include fifty two(52) IO’s per bank. It’s still a multi-SLR device so it’s key to design hardware in the right way to support this architecture.

Prototype design considerations for VU440 Xilinx UltraScale devices

It’s very important for the SLR to IO Bank to Connector mapping to be 1:1 matched. The new HAPS system has again been designed to minimize the detrimental effect of SLR crossing. Signals that cross SLR’s is fine, it’s when the signal makes multiple SLR crossings that you start to notice their effect. The new HAPS system, just like the HAPS-70, has been designed with 1:1 mapping of SLR to IO bank to connector including support for the fifty two(52) IO’s vs. the previous fifty(50) without the need for new accessories. The Hapstrak 3 spec included reserved pins which now support the extra IO.

If your FPGA hardware has connectors that pull in IO across multiple SLR’s you have a very high chance of forcing multi-SLR crossings resulting in much reduced performance.

Mismatched SLR to IO Bank to Connector results in reduced performance

If you select the HAPS-70 or new generation of HAPS utilizing the Xilinx UltraScale VU440 parts then you can expect higher performance operation as this SLR crossing effect is minimized or non-existent.

1:1 mapping of the HAPS-80. SLR to IO Bank to Connector 1:1

You can’t “fix” this in software, this is a hardware artifact which needs to be designed in from the ground up as it has been for the multiple HAPS generations

This is especially important for IP’s. As the SLR’s are so huge in the VU440 it’s possible to fit a whole IP into a single SLR with the IP’s interface going directly to the connector IO’s. *IF* the IP’s interface signals are forced to cross an SLR boundary just to get to connector IO the performance of the IP’s interface is going to be much reduced. IP’s such as USB 3.1, PCIe Gen3 and Gen4 all require interface timing closure above 156 MHz which means they cannot tolerate any SLR crossings for the interface signals to reach the IO.

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