Breaking The Three Laws

 

Intel’s FPGA-Based Prototyping presentations from SNUG Israel

Recently at  SNUG in Israel I was lucky enough to attend two presentations created and delivered by Intel teams on their use of FPGA-based prototyping. The first: “Methodology and Best Practices deployed by Intel for FPGA-based prototyping” discussed various technics they employ to streamline the creation of an FPGA-based prototype. It’s like a mini methodology guide so I highly recommend you review the material.

http://www.synopsys.com/community/snug/pages/proceedingLp.aspx?loc=Israel&locy=2015

Intel presentation from SNUG Israel on FPGA-based Prototyping of SoC's

The second paper titles  “Large Scale IP Prototyping” is a great example of multi-FPGA designs using Synopsys’ HAPS/ProtoCompiler solution and specifically the HAPS High Speed Time Domain Multiplexing to pass ~25K signals between FPGA’s. The material presents Intel’s usage and results and again I recommend downloading and reviewing the material.

http://www.synopsys.com/community/snug/pages/proceedingLp.aspx?loc=Israel&locy=2015

Intel presentation on Large IP Prototyping using HAPS and ProtoCompiler

Oh, you need to have a Synopsys SolvNet ID to download….. Oh#2, I just noticed the proceedings are not posted yet. I am reliably informed that they will be posted shortly.

Many of you know that I travel internationally on business on a regular basis and have asked how I cope with the constant time changes. I employ two simply methods to manage jet lag, #1 No alcohol while traveling at all. This helps when you are only getting 3-5 hours of sleep and #2 Coffee

Best jet lag #2 Coffeeeeee

Luckily while in the UK they serve up vats/buckets of coffee that require two handles to hold the weight. This is a six shot “eye opener”

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