Breaking The Three Laws


Expectation setting for FPGA-based prototyping

The myths of FPGA-based prototyping are still being proliferated and I have taken on a quest to educate the world on what FPGA-based prototyping really delivers. The latest myth propagation is seen below and was cut from a recent posting on a well-known industry website. You are all smart, you will be able to work out where it comes from. Fun read.

Myths of FPGA-based prototyping being propogated

Charlie hits the nail on the head, you need both speed (for Real World IO and OS boot) along with accuracy.

However the comments around it are what I am talking about, they continue to propagate the myths. The top 3 recapped :-

  • Capacity limited to less than 100 Million ASIC Gates
  • It takes months to get prototype working
  • Limited debug visibility

I’ve busted these myths a number of times but you know what they say, tell’em once, tell’em twice, tell’em three times then hit’em with a stick. (ok so I added the stick bit to the saying but that was to increase the humor level of my blogs as some have complained I’m become far too serious)

Capacity is not limited to 100 Million ASIC gates. Proof point: HAPS-70 scales today to twenty four (24) FPGA’s supporting 288 Million ASIC gates and we even have customers successful in prototyping with more FPGA’s. High performance is maintained with operational performance only limited by pin-multiplexing ratio’s. These large sized prototypes can operate in the 10’s of MHz ranges. If I look into my crystal ball (which is very accurate) I see a vision of a HAPS platform supporting in excess of 1 Billion ASIC gates while maintaining scalability and flexibility to support a complete range of designs.

Time to first prototype does not take months, customer usage results with HAPS ProtoCompiler exhibits proven success in as little as one week. The note in the screen shot above says that RTL needs to be rewritten for FPGA, this is not a true fact. Many transformations for FPGA are fully automated in HAPS ProtoCompiler so you maintain a single “Golden” RTL code base.

Debug capabilities have leapfrogged over the last couple of years with HAPS Deep Trace Debug delivering visibility of 1000’s of debug signal bits across multiple FPGA’s and across multiple system setups. While this is not the same level as you have in a simulator or in an emulator you have to remember that you don’t actually need full visibility as typically the RTL being prototyped is more stable as it has passed the block level tests. And just wait and see what my crystal ball is predicting for debug in the next generation of HAPS systems.

So join with me on the quest to rid the world of the myths of FPGA-based prototyping.

  • Become educated: Read the whitepaper dispelling the myths of FPGA-based prototyping
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