Breaking The Three Laws

Archive for 2015
 

Prototyping Low Power Functions Using UPF

Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.

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Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes

 

Understanding Xilinx System Logic Cells vs. Logic Cells

Recently I blogged on a change in the way Xilinx reports the capacity of their new UltraScale FPGA devices. At the end of the blog I left with the following questions

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Posted in UltraScale

 

Performance, Performance, Performance, HAPS with ProtoCompiler Goes to 11

Ultimately when you hand-off your physical FPGA-based prototype to the end users there are only two things that they care about; Performance, Performance, Performance. I know I said there were only two things but performance is so important I listed it three times.

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Posted in HAPS-80, Performance Optimization, UltraScale

 

Part Deux: How many ASIC Gates does it take to fill an FPGA?

Last week’s blog How many ASIC Gates does it take to fill an FPGA? definitely stirred the pot. Part Deux (two?) goes back to basics filling in some gaps and follows up with data supplied by my good friends over at Xilinx.

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Posted in ASIC Verification, FPGA-Based Prototyping, Man Hours Savings, Milestones, Use Modes

 

How many ASIC Gates does it take to fill an FPGA?

How many ASIC Gates does it take to fill an FPGA?

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Posted in Man Hours Savings, Milestones, Project management