Regardless of the market segment your product targets you are being required to build it with the lowest power operation to either compete, differentiate or just be more green. This week I ran into a customer who unfortunately had to re-spin their chip due to a low power mode of operation issue. The software was able to put the chip into a low power mode but due to a bug, they were unable to get the chip out of the low power mode cleanly without a system reset. This customer wanted to better verify the low power modes before tape-out this time around.
Continue Reading...
Posted in ASIC Verification, Bug Hunting, Early Software Development, HAPS-80, HW/SW Integration, In-System Software Validation, System Validation, UltraScale, Use Modes
While traveling this week I found myself explaining the value of Hybrid Prototyping when used with DesignWare IP or your own IP blocks and RTL code. Simply put, using Hybrid Prototyping you can immerse the IP in the context of the SoC without needing to have RTL for the whole SoC. Hybrid Prototyping enables a Pre-RTL SoC representation to be rapidly created (using off the shelf Virtualizer Development kits as a starting point) and incorporating the block(s) under test modeled in HAPS Physical Prototype. This Hybrid Prototype is used for early software development in the case of the DesignWare IP and can be used in the same way for your own blocks in addition to increasing the verification of the design(s) under test.
Continue Reading...
Posted in Debug, DWC IP Prototyping Kits, Early Software Development, Hybrid Prototyping, In-System Software Validation, IP Validation, Man Hours Savings, Use Modes
Recently I blogged on a change in the way Xilinx reports the capacity of their new UltraScale FPGA devices. At the end of the blog I left with the following questions
Continue Reading...
Posted in UltraScale
A while back I wrote about a couple of ways to develop ARM-based software (and other CPU software) using either a physical connection to a hardware board with a CPU subsystem or a Virtual connection to a CPU subsystem using Hybrid Prototyping. I still stand by my conclusion that the Hybrid Prototyping approach provides the most flexibility and is the best solution for early software development.
Continue Reading...
Posted in DWC IP Prototyping Kits, Early Software Development, Hybrid Prototyping, Use Modes
I read an article recently which stated that emulation is the key to Virtual Prototypes, I would like to ride the theme wave and extend the horizon to include FPGA-based prototyping. Back in 2012, Synopsys introduced the first integrated Hybrid Prototyping solution, the combination of Virtualizer Virtual Prototypes and HAPS FPGA-based Prototypes. Our customers recognized a long time ago that the combination accelerates system bring-up by using virtual prototyping for new design blocks or CPU subsystems and FPGA-based prototyping for existing logic.
Continue Reading...
Posted in DWC IP Prototyping Kits, Hybrid Prototyping, Man Hours Savings, Use Modes
LAST CHANCE TO VOTE: The ARM TechCon Innovation Challenge panel has announced the finalists and I am happy to announce that HAPS-80 with ProtoCompiler was selected as one of only twelve. Now it’s your turn to choose the overall winner. Please vote for HAPS-80 FPGA-Based Prototyping system
Continue Reading...
Posted in HAPS-80, UltraScale
The ARM TechCon Innovation Challenge panel has announced the finalists and I am happy to announce that HAPS-80 with ProtoCompiler was selected as one of only twelve. Now it’s your turn to choose the overall winner. Please vote for HAPS-80 FPGA-Based Prototyping system
Continue Reading...
Posted in HAPS-80, UltraScale
Trolling the Xilinx documentation I noticed something amazing while looking at the UltraScale FPGA Product Tables and Product Selection Guide, the VU440 UltraScale device seems to have grown in FPGA capacity. Previously quoted as 4.4M Logic Cells the VU440 is now 5.5M System Logic Cells. Incredible the VU440 is now 25% larger…. Or is it….
Continue Reading...
Posted in UltraScale
The term “Dark Fibre (Fiber) refers to the additional lines/capacity of optical connections a carrier would install when they laid a new pipeline. These unlit optical connections were built in assuming the need for additional capacity in the future. The thinking was that it’s cheaper to do it all at once vs. adding lines/pipelines later. The problem is that this extra capacity is going to waste and while the main carrier was not using it, someone else could have.
Continue Reading...
Posted in FPGA-Based Prototyping, HAPS-80, Man Hours Savings, Milestones, Project management, Tips and Traps, UltraScale, Use Modes
Ultimately when you hand-off your physical FPGA-based prototype to the end users there are only two things that they care about; Performance, Performance, Performance. I know I said there were only two things but performance is so important I listed it three times.
Continue Reading...
Posted in HAPS-80, Performance Optimization, UltraScale
Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.