Breaking The Three Laws

 

Top 3 Myths of FPGA-based prototyping BUSTED

Myth Busted

This week I’ve spent most of my time busting the top three myths of FPGA-Based Prototyping, specifically in respect to the HAPS solution based. The top 3 are:-

  • Capacity limited to less than 100 Million ASIC Gates
  • It takes months to get prototype working
  • Limited debug visibility

These myths are cast backs from the dark ages of FPGA-based prototyping, also known as BMWS, Before Mick Worked at Synopsys, which was a very long time ago, refer to this blog for details http://blogs.synopsys.com/breakingthethreelaws/2014/09/how-to-shaped-the-eda-landscape-and-the-world-we-live-in/

Lets take the first myth: Capacity limited to less than 100 Million ASIC Gates. The HAPS-70 series of FPGA-based prototyping hardware is based on the Xilinx Virtex-7 2000T FPGA’s. Synopsys rates each of these as 12 million ASIC gates, which is a conservative measure coming from years of experience in synthesizing ASIC RTL to FPGA. When the HAPS-70 series was launched back in 2012 Synopsys supported the automated and seamless integration of up to 12 FPGA’s which is equivalent to 144 Million ASIC Gates…. Myth BUSTED !!!! The unique HAPS architecture with its intelligent flexible interconnect architecture (rather than fixed PCB traces), combined with the HAPS proprietary high speed time domain multiplexing, enables the multi-FPGA system to be tailored to the SoC design under test achieving the highest of performance.

But wait…. There’s more….

HAPS External Clock Distribution Board, HAPS-ECDB, automated the integration of up to 24 Xilinx Virtex-7 2000T FPGA's

At the same time that Synopsys launched ProtoCompiler, automated prototyping software for HAPS, we also launched support for up to 288 Million ASIC gates, 24 FPGA’s in a system. ProtoCompiler delivers the design flow managing the large SoC Prototyping project and a HAPS daughter board called the HAPS External Clock Distribution Board, HAPS-ECDB, manages the seamless clocking, reset, configuration and synchronizing across systems. So not only is the myth of capacity limited to 100 Million ASIC gates BUSTED, it’s obliterated. To add credibility to this we even have customers utilizing such systems.

Now for the second myth: It takes months to get prototype working. This problem has been solved with integration between prototyping hardware and software. Even before ProtoCompiler was launched Synopsys delivered Certify automating the flow from ASIC RTL to FPGA-based prototype. To be honest what Certify lacked was a robust partition engine and in-depth integration with the hardware. ProtoCompiler was built with full integration and knowledge of the HAPS hardware target and a partition engine which can leverage the HAPS architecture flexibility. The result is that the time to first prototype (TTFP) can be reduced to as little as a week from first RTL drop…. Myth BUSTED !!!

ProtoCompiler integrated with HAPS delivering Time to First Prototype, TTFP, in as little as 1 week

The great thing is that due to the close integration of ProtoCompiler with HAPS you don’t trade off performance either so the end model still delivers on the #1 requirement of prototyping which is performance.

Time to bust myth 3: Limited debug visibility. First we need to get one thing straight, in FPGA-based prototyping there are hardware limitations as to how much debug data can be stored. While it’s technically possible to get simulator like visibility in HAPS the tracing logic and size of the memory storage needed would make it cost ineffective. But debug visibility is not limited. Take the HAPS-DX, it has built-in HAPS Deep Trace Debug. HAPS Deep Trace Debug is an integrated capability of ProtoCompiler DX combined with the HAPS-DX hardware. You have the capability to do simulator like debug of the design under test. How much debug visibility do you get… well an example is that you can trace 128 signals with a capture rate of 100 MHz hardware speed and you would get 5 seconds of debug data. Or you could trace more signals for a shorter period… I say Myth Busted !!!

But guess what… there is more…..

HAPS Deep Trace Debug with non-intrusive and seamless integration

As seen above, Synopsys also delivers a multi-FPGA solution as part of ProtoCompiler which does not require memory on the HAPS system itself or usage of the Hapstrak connectors. Again this capability is enabled by the tight integration between the ProtoCompiler software and the HAPS hardware systems.

In summary:-

  • Capacity limited to less than 100 Million ASIC Gates – BUSTED !!! Synopsys delivers 288 Million ASIC gate support
  • It takes months to get prototype working – BUSTED !!! ProtoCompiler & HAPS delivers TTFP in as little as 1 week
  • Limited debug visibility – BUSTED !!! ProtoCompiler & HAPS delivers deep trace debug

Are there any more FPGA-based prototyping myths you would like me to bust? Drop me a comment and I’ll work on them

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