Breaking The Three Laws

 

PCIe trends and how to accelerate Gen3 prototyping

Market trends for PCIe between 2013 and 2014

We are seeing PCIe Gen3 being integrated into many different types of SoC’s. The above summarizes the changes we are seeing in the market across 2013 and 2014. One notable area is that PCIe is moving into enterprise storage with PCIe being used for the interface to NAND flash storage devices. The below picture shows the key needs in the segments. PCIe Gen 3 is a great fit for storage as it offers 8Gb/s transport rate across a single lane with x2, x4, x8, x16 lane configurations resulting in huge bandwidth potential. My thanks to Scott Knowlton, of the Express Yourself Blog for the PCIe market data and segment analysis

PCie market segmentation and the main requirements of each

In June 2014 Synopsys ran an internal “FPGA Fest” this is an event where the Synopsys prototyping engineering teams invites all our field application consultant specialists into town for an intensive week of technical training. I attended the training as well and snapped off a couple of pictures of the PCIe Gen3 x4 lane example design training. The design is the DesignWare PCIe Gen3 controller core configured as an end point with x4 lanes. It includes an embedded DMA and software application that enables data to be read/written from and to the prototype. The DesignWare controller IP core is implemented on the HAPS-DX system and interfaces to the PCIe Gen3 capable host via the Xilinx high speed IO’s (Rocket IO transceivers). Don’t forget, I blogged about PCIe Gen3 on HAPS-70 in the past.

Top view of the HAPS-DX plugged into the host

HAPS-DX plugged into PCIe Gen3 capable host

Side view of the HAPS-DX. Here you can clearly see the HAPS-DX kit’s included PCIe Gen3 x8 capable paddle board. This is a daughter board which enables a direct passive connection from the HAPS-DX to the host’s PCIe slot. The paddle board is a highly cost effective way to create the physical link from the HAPS-DX to the host. We offer cabled versions as well which provide greater flexibility in the HAPS-DX placement but at additional cost of course. The SI characteristics of the HAPS PCIe Gen3 paddle board are fantastic (not a technical term I know…) ensuring a stable and robust connection.

View of HAPS-DX PCIe gen3 x8 capable paddle board connected to PCie Gen3 capable host PC

Finally the proof is in the pudding. Here is a picture of the reported bandwidth of the PCIe Gen3 x4 lane connection. WOW, ~700MB/s that’s fast.

Synopsys software application showing results of DesignWare PCIe Gen3 x4 end point running on HAPS-DX. ~700 MB/s fast

Do you want a PCIe Gen3 setup like this? If yes, contact me as we are preparing to release the IP Prototyping Kit for it.

Off subject…. A while back I built a small bird house with my son and he requested we put a label on it saying “Welcome Birds” so the birds would know it was for them. Well as it turns out the sign worked and we have had little birds going in and out all summer. My son said to me last weekend, “Daddy we need to build another bird box for all the other birds” I’ve been busy so to divert his attention I said that if he designed it I would help him build it. 5 minutes later he returns with a piece of paper with the design. He had designed a bird house high rise, yes, a multi-story bird house. Well I promised that if he designed it, we would build it and so here is the result.

High rise or multi-story bird house that Mick Posner built with this son

I should note that his design had way more floors but I negotiated him down to just three. We all love how it turned out. My son helped with the cutting on my radial arm saw, nailing with my framing nail gun, drilling the holes and screwing in the bolts. My father exposed me to tools when I was young, I am trying to do the same in a safe and controlled manor. All the timber used was from the scrap left over from tearing out one of our old fences.

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