Breaking The Three Laws

Archive for 2014

How Proven Solutions Reduce Risk

A couple of weeks back Synopsys announced that we had shipped, to date, over 5000 HAPS systems across more than 400 customers

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Posted in Uncategorized


Recap of what you missed, impactful blogs from the last 3 months

During a customer meeting last week I found myself explaining many different topic’s all of which I have blogged about over the last couple of months. I suddenly realized that while I blog every week that many of you might not get time to read them every week and miss important information. Below is a list of what I think are the impactful blogs from the last couple of months, just in case you missed them.

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Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, HW/SW Integration, IP Validation, Man Hours Savings, Use Modes


Mick’s Projects Update

With it being USA Thanksgiving last week you would think I would have relaxed but I must say I’ve been very busy finishing off a couple of projects. So this week’s blog is on these my latest projects.

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Posted in Mick's Projects


Instant Productivity with IP Prototyping Kits

This week Synopsys announced that we have expanded the IP Accelerated Initiative with New DesignWare IP Prototyping Kits for 10 Interface Protocols 

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Posted in DWC IP Prototyping Kits


FPMM Book Achieves Major Milestone, More than 8000 Copies Distributed

Recently Synopsys promoted that “Synopsys Virtual Prototyping Book Achieves Milestone of More Than 3000 Copies in Distribution to Over 1000 Companies” – Virtual Prototyping continues to gain momentum including Hybrid Prototyping, which combines Virtual Prototyping with FPGA-based prototyping. The VP book statistics prompted me to have a look at the FPGA-based Prototyping Methodology Manual, FPMM statistics.

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Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, IP Validation, Technical, Tips and Traps


Dr. Lauro Rizzatti please read my blog, your information is out of date

–//–//–//–//–//–//–//–//–//–//– Dear Dr. Lauro Rizzatti,

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Posted in ASIC Verification, Debug, Man Hours Savings


3 Phase Approach to Successful Prototyping

In previous blogs I have spoken a lot about automation, features and capabilities which accelerate time to operational prototype and deliver higher performance enabling you to run more software against your design representation. These capabilities are designed to reduce the need for prototyping expertise and effort……..  but not to zero. Anyone who tells you that no expertise or effort is needed is not telling you the whole truth. This was the basis of this blog, “Breaking the three laws” of which the first law is ASIC are FPGA Hostile! Who can tell me what the other two laws are? I know but this is like a quiz for my readers.

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Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, Technical, Tips and Traps


SW Dev Env using ARM-based daughter board directly vs. Hybrid Prototype

This week’s blog is a bit of a mashup (Yes that is a real word, a mashup, in development, is something that uses content from more than one source to create a single new offering) as I am pulling together two topics to create one. The #1 usage case of prototyping is for early software development. You can do this very early, pre-RTL using Virtual Prototypes, later in the design cycle with FPGA-based Prototypes but it’s the bit in the middle that this week’s blog examines.

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Posted in ASIC Verification, Daughter Boards, DWC IP Prototyping Kits, Early Software Development, Hybrid Prototyping, IP Validation


Abstract Partition Flow Advantage

It’s the age old question, what came first, the chicken or the egg?

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Posted in Man Hours Savings, Mick's Projects, System Validation, Use Modes


Rabbets, the Importance of Bank/SLR 1-1 mapping and Certify 2014.09

Rabbets, the Importance of Bank/SLR 1-1 mapping and Certify 2014.09, starting in reverse order this week.

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Posted in Daughter Boards, Man Hours Savings, Use Modes