A couple of weeks back Synopsys announced that we had shipped, to date, over 5000 HAPS systems across more than 400 customers Synopsys Ships Over 5,000 HAPS Prototyping Systems for Software Development, HW/SW Integration and System Validation HAPS FPGA-based Prototyping Systems Help More Than 400 Companies Accelerate Time to First Prototype and Avoid Costly Device […]
Posted in Uncategorized | Comments Off on How Proven Solutions Reduce Risk
During a customer meeting last week I found myself explaining many different topic’s all of which I have blogged about over the last couple of months. I suddenly realized that while I blog every week that many of you might not get time to read them every week and miss important information. Below is a […]
Posted in ASIC Verification, Bug Hunting, Daughter Boards, Debug, HW/SW Integration, IP Validation, Man Hours Savings, Use Modes | 1 Comment »
With it being USA Thanksgiving last week you would think I would have relaxed but I must say I’ve been very busy finishing off a couple of projects. So this week’s blog is on these my latest projects. Firstly I put the finishing touches on the Sauna which was a birthday gift for my wife. It’s […]
Posted in Mick's Projects | Comments Off on Mick’s Projects Update
This week Synopsys announced that we have expanded the IP Accelerated Initiative with New DesignWare IP Prototyping Kits for 10 Interface Protocols IP Prototyping Kits enable designers to accelerate prototyping, software development and integration of IP into SoCs Supported protocols include USB 3.0, SSIC, PCI Express 2.0, PCI Express 3.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI […]
Posted in DWC IP Prototyping Kits | Comments Off on Instant Productivity with IP Prototyping Kits
Recently Synopsys promoted that “Synopsys Virtual Prototyping Book Achieves Milestone of More Than 3000 Copies in Distribution to Over 1000 Companies” – http://news.synopsys.com/2014-11-05-Synopsys-Virtual-Prototyping-Book-Achieves-Milestone-of-More-Than-3000-Copies-in-Distribution-to-Over-1000-Companies Virtual Prototyping continues to gain momentum including Hybrid Prototyping, which combines Virtual Prototyping with FPGA-based prototyping. The VP book statistics prompted me to have a look at the FPGA-based Prototyping Methodology Manual, […]
Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, IP Validation, Technical, Tips and Traps | 1 Comment »
–//–//–//–//–//–//–//–//–//–//– Dear Dr. Lauro Rizzatti, I enjoyed reading one of your recent articles http://electronicdesign.com/eda/hardware-emulation-weapon-mass-verification but was dismayed that you were still quoting limitations from the early years of FPGA-based prototyping. I recommend you refresh your knowledge and read my recent blog on the top myths of FPGA-based prototyping busted. http://blogs.synopsys.com/breakingthethreelaws/2014/09/top-3-myths-of-fpga-based-prototyping-busted/ I’m looking forward to […]
Posted in ASIC Verification, Debug, Man Hours Savings | Comments Off on Dr. Lauro Rizzatti please read my blog, your information is out of date
In previous blogs I have spoken a lot about automation, features and capabilities which accelerate time to operational prototype and deliver higher performance enabling you to run more software against your design representation. These capabilities are designed to reduce the need for prototyping expertise and effort…….. but not to zero. Anyone who tells you that […]
Posted in FPGA-Based Prototyping, FPMM Methods, Getting Started, Technical, Tips and Traps | Comments Off on 3 Phase Approach to Successful Prototyping
This week’s blog is a bit of a mashup (Yes that is a real word, a mashup, in development, is something that uses content from more than one source to create a single new offering) as I am pulling together two topics to create one. The #1 usage case of prototyping is for early software […]
Posted in ASIC Verification, Daughter Boards, DWC IP Prototyping Kits, Early Software Development, Hybrid Prototyping, IP Validation | 1 Comment »
It’s the age old question, what came first, the chicken or the egg? When we ask this question about FPGA-based prototyping then the answer uncovers some interesting facts about the evolution of this technology. When first utilized most customers would build their own boards and tailored them to the exact SoC project’s needs. The advantage […]
Posted in Man Hours Savings, Mick's Projects, System Validation, Use Modes | Comments Off on Abstract Partition Flow Advantage
Rabbets, the Importance of Bank/SLR 1-1 mapping and Certify 2014.09, starting in reverse order this week. Certify 2014.09 is now available and we’ve packed it with new capabilities. Below is just a snippet of the new additions. Advanced synthesis options deliver improved timing QoR, correlation and rapid timing closure. On average 5-6% timing QoR improvement. […]
Posted in Daughter Boards, Man Hours Savings, Use Modes | Comments Off on Rabbets, the Importance of Bank/SLR 1-1 mapping and Certify 2014.09
Michael (Mick) Posner joined Synopsys in 1994 and is currently Director of Product Marketing for Synopsys' DesignWare USB Solutions. Previously, he was the Director of Product Marketing for Physical (FPGA-based) Prototyping and has held various product marketing, technical marketing manager and application consultant positions at Synopsys. He holds a Bachelor Degree in Electronic and Computer Engineering from the University of Brighton, England.
