This week I was asked to compare the Synopsys HAPS systems to FPGA vendor evaluation boards. I only have good things to say about the FPGA vendor evaluation boards but when comparing these evaluation boards to HAPS for serious FPGA-Based Prototyping I just said, “That’s like using a hammer to put in a screw”. A hammer is a great tool but it’s not the right tool for the job. Evaluation boards are not designed with FPGA-Based prototyping in mind, they are designed to enable evaluation of the individual FPGA devices capabilities. “Evaluation” board, not FPGA-based prototyping system. HAPS is architected with the FPGA-based prototyping in mind and provides the capabilities to increase the customer’s productivity. Our goal is to improve the customer’s efficiency by providing out-of-the-box capabilities which the customers can deploy immediately. To meet the demands of FPGA-based prototyping the customer would need to hand craft such capabilities for an evaluation board and then internally support it’s usage which detracts the customer from the important tasks such as early software development, hw/sw integration and creating product differentiation.
Hot on the heels of last week’s blog on the common mistakes first time prototypers make, Synopsys published a white paper titled “My RTL is an Alien!”.
I was recently talking to a customer who found that deploying FPGA-based prototyping was a challenge. This was a customer who had only every done simulation for verification purposes. Their last chip incorporated dual embedded processors and unfortunately they had to re-spin the silicon due to a hardware bug that they found only when running the real software. This bug was devastating, the cost was huge as it included the physical costs of the re-spin but worst was the revenue hit from being late to market. This company knew it had to adopt FPGA-Based Prototyping to enable early software development, HW/SW integration and System Validation all PRE-SILICON. The goal was to run the actual software against the hardware and identify HW/SW bugs before code freeze and tape-out.
Posted in ASIC Verification, Debug, FPGA-Based Prototyping, FPMM Methods, Getting Started, In-System Software Validation, Project management, Technical, Tips and Traps | Comments Off on Do you have what it takes to be a prototyping super hero?
FPGA-based prototypes offer tremendous value for system-on-chip validation and hardware/software integration by delivering high capacity, fast clock performance, and real-world I/O connectivity. The combination of performance and high-fidelity makes software integration and development tasks feasible months before test silicon is available. But when something goes wrong, debugging a complex prototype can be challenge.
Over the last two weeks I’ve been traveling in China and Taiwan talking to FPGA-Based Prototyping users at the two Synopsys User Group, SNUG, events. FPGA-based prototypes in these regions are used to validate all types of designs from smaller RTL blocks to video cores and mobile application processors. The engineers face the same challenges as engineers in the rest of the world, mainly in the area of converting ASIC RTL to FPGA images.
Guest Blog Alert – Doug Amos, author of the FPGA-based Prototyping Methodology.
Last week’s blog was on hitting your milestones and I had communicated that FPGA-based prototyping is used to find design bugs. A follow on question was submitted which basically read “great so you have found a hardware bug but how do you track down the source of that bug?”
This week I had to explain why FPGA-based prototyping is used. (I had to remind myself that not everyone lives and breathes FPGA-based prototyping day in day out like I do) The explanation was for an exec so I had to ensure the explanation was clean and sharp. I simply said “FPGA-based prototyping helps you meet your milestones, both for hardware development and the software development”. This caught their attention so I expanded the answer with
Including USB in this week’s blog title was designed to be catchy and an effort to grab a couple of Eric Huang’s USB Blog’s bazillion readers. It’s not really the demise of USB but more of the demise of a single USB stick. I tend to destroy pens and papers by playing with them while I work, this week I found myself destroying a perfectly good USB stick.
In my final installment on RTL Block Validation we are going to talk about the Hybrid Prototyping usage case.