Breaking The Three Laws


Xilinx FPGA’s for FPGA-Based Prototyping

If we look at the FPMM survey respondent data it’s clear to see that the favored FPGA device for FPGA-based prototyping is Xilinx devices

This week Xilinx announced the Virtex® UltraScale™ VU440 3D IC.

This is the device that Xilinx wants the future generation of FPGA-based prototyping hardware to make use of. Rather than spending too much time picking apart the announcement I’m going to try and summarize it in my own words. Then I’m going to share my blog with friends over at Xilinx and request that they expand on my points and add anything that I missed in a guest blog.

In my humble opinion the key capabilities specific to FPAG-based prototypers are:-

  • Capacity
  • Routing resources
  • Clocking structure

So starting with capacity, the VU440 is a whopper of a large FPGA, Xilinx claims 50 Million equivalent ASIC gates. I think this claim is a bit of a whopper, as in I personally do not think that you could map a 50 Million ASIC gate design into this device. Each FPGA vendor counts ASIC gate equivalent slightly differently so it’s very hard to compare ASIC technology gates to FPGA equivalent ASIC gates. For example Synopsys uses the Xilinx Virtex-7 2000T in its HAPS-70 series and we publicize 12 Million ASIC gate capacity per FPGA. This calculation of ASIC gates has come from the 10+ years of experience in FPGA-based prototyping. We claimed 2 million ASIC gate capacity of the Virtex-5 330, 4.5 million ASIC gates for the Virtex-6 760 and as stated above, 12 million ASIC gates for the Virtex-7 2000T. Our customers don’t complain that their ASIC RTL does not fit into our systems so we feel confident that our calculation of ASIC gate equivalent is pretty spot on.

Regardless of the ASIC gate counting differences the VU440 is over double the size of the 2000T meaning that we expect it to provide over 25 Million ASIC gate capacity per FPGA. This is great for FPGA-based prototypers as by the time this device is available the designs being prototyped will need this capacity increase. During the transition from V5 to V6 and V6 to V7 we saw no consolidation of systems, as in for example a customer using a dual FPGA system did not move to a single FPGA system with the new FPGA which had double the capacity, they moved to the dual FPGA system with the new FPGA. Some customers even moved to larger systems such as from the 4 to the 8 FPGA system. This tells me that the size of the designs was scaling at a faster rate than the FPGA technology. I expect this to be true in the future to.

Routing resources is very important to FPGA-based prototyping as the code that is being thrown at these devices is ASIC RTL and not specifically “tuned” for FPGA. The requirement of translating ASIC RTL to FPGA is driving the need for prototyping specific software tools that are geared towards solving this ASIC to FPGA translation with reduced turn-around. While FPGA implementers who’s final product utilizes the FPGA device prototypers mostly don’t care what the device is they want to get a model up and running fast so they can quickly enable their software developers. Look at the FPMM survey responses below, mapping ASIC RTL to FPGA is still the #1 challenge by a long way. I’m going to blog about this need more in the future.

Staying on track with routing Xilinx states that the new VU440 has a greater number of passive interposer interconnect (features 5x more inter-die bandwidth). This is a 3D device so it has multiple Super Logic Regions (SLR’s) which connect to each other via this passive interconnect. With more interconnect the users should see faster fitting times, (FPGA Place & Route) from the higher number of possible solutions available. This increased interconnect should also result in greater utilization (Xilinx claiming up to 90%) which means you can stuff more into the device.

Finally clocking, Xilinx is claiming “ASIC like” new clocking structures and clock routes that span SLR boundaries. This is really important to FPGA-based prototypers as the code that is being targeted to these devices is ASIC RTL so by nature is designed with ASIC style clock trees. With the new Xilinx architecture being closer to ASIC clocking the designs *should* translate better into the FPGA device. Don’t take my word for it, look at the FPMM survey responses below, translating ASIC clocks to FPGA is the #2 challenge identified. Xilinx’s ASIC like clocking will potentially ease the support for ASIC clocking structures and with the new higher number of available clocks even ASIC’s with thousands of clocks should be easier to target to this new FPGA.

This combined with the clocks that now span SLR boundaries means that higher performance should be achievable. Of course don’t forget that the overall system performance of an FPGA-based prototype is usually not dictated by the single FPGA performance but by the interconnect between the FPGA’s and the pin multiplexing (when you have more signals between FPGA’s than pins). This is why Synopsys offers HAPS High Speed Time-Domain Multiplexing, HAPS HSTDM, which packages up signals and transfers them between FPGA’s are Gigabit speeds. The use of HAPS HSTDM is almost transparent to the users when they use the Synopsys tools which automate the insertion of the HAPS HSTDM IP.

WOW, this blog got long…….

So to summarize the new Xilinx UltraScale VU440 FPGA looks like it will be very exciting for FPGA-Based Prototypers. I am also looking forward to seeing how Altera responds to this <insert evil grin here>.

What is your opinion of the new Xilinx device? Post a comment and let me know.

Now off topic, I finished the toy I have been making for my son, the Command Module. I think it turned out very well. It has plenty of switches, dials and interactive buttons to ensure that when mixed with a little imagination it can be turned into anything my son can think of. Here is a video of it in action:

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