Posted by Michael Posner on November 29, 2013
While wandering though the DesignWare IP testing lab in our office I found this:-
It’s sort of hard to see but this is a HAPS-70 S12 platform connected to a LeCroy PCIe protocol and electrical compliance tester. The DesignWare PCIe controller core has been implemented in the FPGA and in this setup is using the FPGA devices transceivers for the electrical interface. The split between the DesignWare controller and the Xilinx transceivers is at the PIPE interface.
The pod sitting on top of the HAPS-70 is the Universal Multi-Resource Bus pod, which enables remote access, high speed configuration and dynamic debug capabilities.
I’m pretty sure the setup was being used for PCIe Gen 3 compliance testing in preparation for an upcoming PCIe SIG meeting.
The DesignWare PCIe core is designed for SoC usage and the testing on the HAPS platform provides a reference that the core has been hardware validated and compliance tested. This is of course without having to harden it in silicon so the HAPS setup is a far more flexible solution for the digital controllers. It was great to see the HAPS technology being used to benefit our own teams at Synopsys.
Short blog this week as I am currently digesting turkey from the USA thanksgiving and need to take a little nap.