I’ve talked about streamlining IP to SoC prototyping and the use modes that prototypers use for IP validation. This week Synopsys announced the new HAPS Developer eXpress (HAPS-DX) prototyping system. This new HAPS-DX system is perfect for complex IP and subsystem prototyping and ties in nicely with the flow that I have been blogging about for streamlining IP to SoC. Similar to what I did last week with the Xilinx press release I thought I would do a tear down and cut to the chase and detail how HAPS-DX will benefit you.
If we look at the FPMM survey respondent data it’s clear to see that the favored FPGA device for FPGA-based prototyping is Xilinx devices
It’s been a quiet week for me and prototyping but I did talk to an engineer about command and control of an FPGA-based prototype which I thought was quite interesting I will share the story.
While wandering though the DesignWare IP testing lab in our office I found this:-
Posted in ASIC Verification
This week I wanted to focus on a discussion around prototyping hardware assembly.
I don’t know about you but this has been a whirlwind week for me. I was at the corporate Synopsys offices in Mountain View CA working with the HAPS hardware and software development teams. I also video interviewed Eric “Hollywood” Huang on the DesignWare 10G USB 3.1 teams use of the HAPS-70 systems. We will edit and post that video in a couple of weeks. I was making fun of Eric because he is always doing videos and it looks so easy. I have to say doing videos is not easy as Eric makes out. Kudos to him.
Posted in Debug
As we all know FPGA-based prototyping enables early software development, HW/SW integration and system validation but did you also know that HAPS FPGA-based prototyping is also designed to make Eric Huang, PMM for USB IP at Synopsys famous? I’ll be honest, when we designed the HAPS-70 systems we did not highlight this as part of the MRD which shows that sometimes capabilities evolve on their own.
A couple of folks complained that my last blogs have been a bit long and boring. (Boring! Me?) So I would like to start this week and apologize to all my 5th Grade readers, I’ll try harder in the future to use smaller words and more pictures.
I noticed that Synopsys launched the new Verdi3 which provides the capability to debug both the hardware RTL code and the Software C code. Here is a video demo of the new capabilities: http://www.synopsys.com/Tools/Verification/debug/Pages/verdi-hw-sw-debug-video.aspx
Of course I am talking about the MIPI protocols and not something you can catch from too much internet. I’ve blogged about MIPI and FPGA-based prototyping before but I felt it was time to talk about MIPI again as it’s exploding all over the mobile market. In addition to the well know MIPI specifications for Camera and Display interfaces, CSI and DSI you now have UFS for mass storage, High Speed Synchronous, Low latency, Peripheral interface and the list goes on.