While I was on vaction I promised that the blog would be populated with fact filled articles created by a set of talented guest bloggers. Nice job team, no one posted! That’s the bad news, the good news is that they will no longer make fun of me for my postings questioning my sense of humor and understand that owning a blog is not as easy as it first seems.
Did you know that the team responsible for Synopsys’ FPGA-based prototyping products has been innovating for over 10 years?
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DisplayLink is a semiconductor and software company that enables virtual graphics connectivity between computers and displays. DisplayLink make use of both the Synopsys DesignWare IP for USB 3.0 and HDMI in addition to HAPS FPGA-based prototyping systems. Synopsys recently published a success story on their success. The full success story can be found here, below is an extract in respect to their use of the HAPS FPGA-based prottyping systems. To reduce the design risk inherent in implementing an evolving standard, DisplayLink used Synopsys’ HAPS FPGA-based Prototyping System to validate the functionality of their design and to develop software in parallel with the ASIC development. On a large SoC it is critical to ensure communication between analog PHYs and digital logic. By using the HAPS USB 3.0 PHY daughter card, the DisplayLink design team was able to validate the working system at almost real-time speeds, months ahead of silicon availability, and debug software well before tape out. They had the added benefit of being able to demonstrate the end product to customers long before silicon came back. “It’s an incredible value proposition to be able to not just tell our lead customers that the design will work, but to demonstrate it on a prototyping platform for them to see with their own eyes,” said Jonathan Jeacocke, vice president of Engineering, DisplayLink. “By using HAPS, we had absolute confidence that the final silicon design would work the very first time.” It’s great to hear that the HAPS systems are providing so much value to DisplayLink.
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In a related question (refer to my previous blog post) what I/O interfaces do you utilize on your FPGA-based prototype and what are you using that interface for? Below is the latest snapshot of interface usage from the FPMM survey data.
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While reading through the latest FPMM survey data I stopped and reviewed in detail the type of memories used.
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Great news, Synopsys has signed a definitive agreement to acquire SpringSoft. Springsoft is well known for its highly successful line of ASIC debug and custom implementation tools but not many people know that Springsoft also offers a debug solution for FPGA-based prototypes. Springsoft’s Protolink product is a system that enables their Verdi automated debug tool be used for FPGA-based prototyping hardware debug. Springsoft promotes some key capabilities that reduce the turn-around time to add/change probes as well as an external memory card that enables a deep history of signal data to be captured at prototyping speeds.
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I have many things to cover in this week’s blog, first is nothing to do with FPGA-Based Prototyping, it’s a shout out to my friend Eric Huang. Eric is the Product Manager of the DesignWare IP for USB 3.0 products and the source of my amusement last week. The same week Eric had a biking accident which was bad enough that he was rushed to hospital in an ambulance. Eric is back at work but I urge you to wish Eric all the best by posting comments in his Blog, To USB or Not to USB. Wishing you a speedy recovery Eric.
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I sometimes forget the key value of FPGA-Based Prototyping and get carried away with discussing advanced capabilities such as Hybrid Prototyping, Co-Simulation and Synopsys’ UMRBus. The good news is that Eric Huang over in DesignWare IP for USB 3.0 land has not. Eric is a man of many talents and loves to be in front of the camera. I make fun of him for this but that’s only because I’m jealous of his skills.
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I was recently asked for my recommendation on what needed to be designed into FPGA-based prototyping hardware to enable high performance. This is one of my favorite topics as the answer is almost always a surprise. Prototyping performance is a measure based on design requirements and goals and while 50 MHz may seem slow to some it can be very fast for others and meet all their requirements. Lets have a look at an updated pie chart of prototyping performance from the FPMM survey data to see what engineers are achieving.
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Based on the title of this blog you can see why I work in the EDA industry, I’m no lyric writer. There is a reason behind the title though, I am not the only one who thinks Hybrid Prototyping is a great solution enabling earlier prototype availability meaning you can start software development earlier.
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