Breaking The Three Laws


What type and how do you use memory interfaces?

While reading through the latest FPMM survey data I stopped and reviewed in detail the type of memories used.

The list of memories got me wondering what they are being used for, as in, are they part of the design or are they being used as a buffer or data storage? These are the two usage cases for memories that we see all the time.

For example if your design includes a DDR 3 memory controller such as the DesignWare Universal Memory Controller, when you integrate it into the FPGA-based prototype you will have it interface with some type of physical memory. In the case of the DesignWare Universal Memory Controller the DWC IP team provides an example FPGA-based prototyping PHY model which connects the controller to the FPGA’s I/O’s enabling it to interface with a real DDR3 memory on a daughter board such as the HAPS High Speed DDR3 daughter board. This usage case is the design specific case, the memory is required for interfacing to a block of the actual design.

The second usage case is when the memory is being used to store test data. An Example is when DDR memory is used to store video graphics frames so they can be streaming into the prototype at speed. External memory is also used to extend the signal debug visibility buffer as part of the HAPS Deep Trace Debug capability. This usage is not design specific, it’s prototyping task or debug specific.

So my question, what types of memory do you interface with and what usage model are being employed?

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