Posted by Michael Posner on July 25, 2012
I have many things to cover in this week’s blog, first is nothing to do with FPGA-Based Prototyping, it’s a shout out to my friend Eric Huang. Eric is the Product Manager of the DesignWare IP for USB 3.0 products and the source of my amusement last week. The same week Eric had a biking accident which was bad enough that he was rushed to hospital in an ambulance. Eric is back at work but I urge you to wish Eric all the best by posting comments in his Blog, To USB or Not to USB. Wishing you a speedy recovery Eric.
Last week Ed Sperling summarized my blog as follows:
Synopsys’ Michael Posner pays homage to one of his colleagues and fellow bloggers, Eric Huang—who was alive and well at last sighting—while focusing at least tangentially on FPGA prototyping. We’re not quite sure of the real purpose of this blog, but it’s hard to stop laughing.
Thanks Ed, I think that was a complement. Of course did you know that Eric had injured himself? If not you have some serious physic skills.
Onto business. This week I was asked if there was a way to quickly validate that a block modeled in an FPGA-based prototype was functionally correct? The issue the user was trying to solve was the verification of the DUT’s functionality in its FPGA-based prototyping form BEFORE it was rolled out for SoC validation and SW development tasks. To date the user would have to re-create the golden simulator regression testbench in a format that they could execute against the FPGA-based prototype. This was a large effort as the golden simulation regression test suites are typically very comprehensive. The user wondered if there was a better way to do this?
The Answer is YES, HAPS Co-Simulation.
The HAPS FPGA-based prototyping systems offer a Co-simulation capability which enables a simulator testbench to drive the DUT with the HAPS system over a cycle accurate interface. This flow is automated so it’s relatively easy to take a block from RTL to HAPS and then verify it’s function against its original golden simulation regression test bench. This is ultimate re-use, the user does not have to create a new specific FPGA-based test bench to test the DUT model, just re-use what the RTL verification team has already created. Not only does this reduce the effort of the FPGA-based prototype bring up but the user can further test the DUT in this high performance environment.
Typical design flow for HAPS Co-Simulation
Great right? Well the user was still worried, they wondered how stable this HAPS Co-Simulation flow was? The answer is it’s very stable. We introduced HAPS Co-simulation capabilities as part of the HAPS-60 launch back in 2010. The underlying capability and UMRBus technology was part of the CHIPit products so have been available for many years before that.
Do you have questions on FPGA-based prototyping? Post a comment and I’ll do my best to answer
I have some much needed vacation time coming up so look out for future postings by some guest bloggers. Please be nice to them.