Dear reader, With DAC just around the corner, those planning to attend are probably already calculating their optimal route through the maze of booths, panels, papers and of course the parties. FPGA-based prototyping is likely to have its strongest DAC ever, and Synopsys is doing its bit to carry on the good work.
As agreed at a recent SNUG tutorial, a best-of-both-worlds approach is to use more automation and compromise in order to get something running at low performance in a few weeks but then to re-iterate to meet the real performance goal needed later in the project.
However, beware of dead-ends.
In recent discussions with eminent prototypers at SNUG San Jose and back here in Europe, I have been interested to know how mature and complete the design must be in order to make prototyping worthwhile. I have heard good arguments for waiting until the RTL is frozen, but also for starting as soon as possible because even partial RTL will help to “pipe-clean the flow”. Is there an optimal midpoint?
With the 600+ downloads of the FPMM eBook already, and the survey data provided, readers have provided a fascinating new snapshot of today’s prototyping projects.
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Apparently, there was some kind of announcement today about a tablet computer or something like that. At the same time, there has been another announcement today and here is the summary….
A short post explaining the title of this blog and introducing the Three Laws of Prototyping.
Posted in FPGA-Based Prototyping | Comments Off on So, what are these Three Laws all about?
This is just an opener to set the stage for this new blog about FPGA-based Prototyping.