Merry Christmas to all our fellow prototypers!
I looked it up in Webster; yes “combinatorially” is a real adverb.
There are those who say that one should partition so that only sequential eements are allowed to appear at the FPGA edges, thus simplifying the timing and constraints at the FPGA pins.
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The North American leg of our FPMM Workshop world tour is over and what a brilliant series it has been so far! I have met prototypers working on many different projects; some new to prototyping, some very experienced, but all looking to make connections and share best practices with other prototypers in their area.
Posted in FPGA-Based Prototyping | Comments Off on Meet the Prototypers #2: Configuration and debug of PCIe in the lab
Blimey, there are a lot of prototypers out there!
Problem: How do you start live tests of the new DVB-T2-Lite standard within days of it being approved?
Posted in FPGA-Based Prototyping | Comments Off on Meet the Prototypers #1 : Prototyping enables immediate BBC Demonstration of DVB-T2-Lite
It was the eminently quotable William Shakespeare who wrote “some are born great, some achieve greatness and some have greatness thrust upon them.” The quote comes from Twelfth Night, by the way.
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Look who I met at DAC yesterday, Andrew Dauman, VP of Engineering for FPGA at Synopsys and Neil Songcuan, Product Manager of the Synopsys HAPS hardware.
Posted in FPGA-Based Prototyping | Comments Off on HAPS Chaps
Here is a short summary of my first days impression from DAC 48 gained from walking the exhibit hall. The amount of FPGA-based prototyping hardware being exhibited has definitely increased over previous years. This is in respect to both the number of explicit vendors directly involved in FPGA-based prototyping and the vendors that are utilizing an FPGA-based prototyping platform to demonstrate their capabilities or IP. This really reflects the importance designers get and see in FPGA-based prototyping. The HAPS hardware is on display right at the front of the Synopsys booth, very eye catching.
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