Breaking The Three Laws

Hitting the Mark

Just in case you had not noticed, the prototyping blog can now be found here: https://blogs.synopsys.com/hittingthemark/ Talking of hitting the mark, I recently took up archery using a re-curve bow. I started in March 2016 and now in July after practicing about once a week I think I’m starting to get more consistent. Below is […]

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Read Issue #1 Prototyping Newsletter: Reduce Risk and Speed Time-to-Market with End-to-End Prototyping

We have just published the first issue of our new prototyping newsletter. This quarterly newsletter provides you with the latest information on end-to-end prototyping, including in-depth technical articles, white papers, videos, webinars, product announcements and more.  As the industry’s number one provider of architecture design, virtual and physical prototyping solutions, Synopsys is committed to providing you […]

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Which is your favorite FPGA-based prototyping setup?

Interesting article posted to eetimes this week, 10 Favorite FPGA-based Prototyping Boards, I would actually argue that only the #1 listed solution, HAPS with HAPS ProtoCompiler is a comprehensive FPGA-based prototyping solution. The others all serve a purpose but typically have no specific features facilitating FPGA-based prototyping. HAPS with HAPS ProtoCompiler you get the following […]

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Innovation Increases Design Visibility and Boosts Performance of FPGA-based Prototypes

I just noticed (late) that the latest release of HAPS ProtoCompiler, 2016.03 is available. The new release can be found under SolvNet here. (A SolvNet ID and a valid HAPS ProtoCompiler license will be needed for download.) The new release includes capabilities which reduce the time to first prototype even more than we do today, […]

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Verifying Power Management Modes, both Software and Hardware

Quote: “It works! After disabling power management for my WiFi stick in Raspberry PI configuration it is now working!!” BTW: This blog was inspired by a true story of a challenge that Achim Nohl, Technical Marketing Manager for HAPS Physical Prototyping recently experienced: https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=51543 Power management is an increasingly complex function provided by hardware and controlled by a […]

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ESD Precautions Essential for prototype handling

Thanks to my latest project, a home built Van De Graaff generator, it reminded me to post some more information on ensuring you take ESD precautions while handling your physical prototyping hardware. These are essential when handling Xilinx Virtex-7 and UltraScale based platforms, ensuring you don’t let the magic blue smoke escape. First read my […]

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Prototyping enables worlds first PCIe Gen4 (16 Gb/s) demonstration

While roaming the halls of Synopsys corporate offices I found myself in one of the smaller demonstration labs and spotted this: This is the demo setup for the DesignWare IP for PCIe Gen4 which is the latest and fast 16 Gb/s PCIe transfer solution. (Sorry for the low quality mobile phone pic). This is the […]

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It’s not too late to attend SNUG Silicon valley

Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx Prototyping topics: Techniques Used to Partition a Complex-SoC into Multi-HAPS-70 System FPGA Debug: Improving Debug Turnaround Time in High Speed Designs Accelerate Your Prototyping Productivity Leveraging HAPS Integrated Prototyping Solution Adapt, Port, and Integrate Quickly – Prototyping the Right Way Address TTM by Prototyping […]

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What’s in it for me? The market shift to integrated Physical Prototyping

FPGA-based physical prototyping is the go-to standard for high-performance, high-productivity verification, debug, and software development on many electronic systems today. But, it is becoming increasingly difficult to put together an ad-hoc prototype mixing pieces from various vendors with home-grown components. With the complexity of today’s systems, an integrated prototyping system can bring significant advantages. Learn […]

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Debug: Zero in on Defects Using Global State Visibility & Other High Visibility Capabilities

Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which […]

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