Breaking The Three Laws

Just in case you had not noticed, the prototyping blog can now be found here: https://blogs.synopsys.com/hittingthemark/

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Interesting article posted to eetimes this week, 10 Favorite FPGA-based Prototyping Boards,

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I just noticed (late) that the latest release of HAPS ProtoCompiler, 2016.03 is available. The new release can be found under SolvNet here. (A SolvNet ID and a valid HAPS ProtoCompiler license will be needed for download.)

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Quote: “It works! After disabling power management for my WiFi stick in Raspberry PI configuration it is now working!!”

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Thanks to my latest project, a home built Van De Graaff generator, it reminded me to post some more information on ensuring you take ESD precautions while handling your physical prototyping hardware. These are essential when handling Xilinx Virtex-7 and UltraScale based platforms, ensuring you don’t let the magic blue smoke escape.

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While roaming the halls of Synopsys corporate offices I found myself in one of the smaller demonstration labs and spotted this:

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Hey, it’s not too late to attend SNUG Silicon Valley: http://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx

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Design defects (bugs) can be introduced at multiple levels in the design process from RTL defects, SW defects and Integration defects. The key to rapidly locating these bugs is to tailor the debug strategy to the type of bugs you are looking for. Depending on where you are in the design cycle usually dictates which type of bug is more prevalent. Physical Prototyping exercises the RTL, SW and the fully integrated design so is a key technology for design verification. Having the right debug tool set if critical to accelerate the verification task.

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