SAE is Free!
Hello everyone,
Posted in AMS Circuits, analog, analog design, Fast-SPICE, HSPICE, SPICE, verification |
Is Your MOSFET Suffering the Effects of Aging?
Hello everyone,
Posted in analog, analog design, Device Modeling, digital, Fast-SPICE, HSPICE, Nanometer CMOS, Reliability, SPICE, verification |
DAC 2015 Synopsys Circuit Simulation Luncheon: Altera, ST, TSMC and Xilinx on Synopsys Industry Leading Performance for Analog Mixed-signal Designs
Improving the performance of existing technologies has always been a key element in the development of computational systems and EDA tools. However, as analog mixed-signal designs complexity drastically increases, conventional techniques are becoming outdated and new technologies must be adopted by designers.
Posted in AMS EDA tools, EDA, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, verification |
VCS AMS at DVCON : Xilinx talk, demos, technical sessions and much more :)
Happy Friday,
Posted in Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification |
Synopsys AMS SIG Event in Bangalore, India – ADI, ARM, ST and Xilinx present their latest solutions to resolve today analog mixed-signal challlenges
Happy new year everyone,
Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification |
VCS AMS joint webinar with Synopsys, ST and ARM : latest insights on advanced mixed-signal verification
Happy Tuesday,
Posted in AMS Assertions, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification |
DAC 2014 AMS panel videolog now available
We hosted a few weeks ago at DAC Synopsys AMS luncheon with speakers from Micronas, Infineon, AMD and ST. The theme of this year’s event was “Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier”.
Posted in AMS Circuits, AMS EDA tools, analog, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification |
DAC Synopsys AMS Technical Luncheon Panel – Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier
DAC is here and we are ready!
Posted in AMS Circuits, AMS EDA tools, Mixed Signal/Cosimulation, Uncategorized, verification |
VCS AMS – Synopsys advanced mixed-signal verification solution to accelerate regression testing of mixed-signal SoCs
You may have seen Synopsys recent announcement during SNUG:
Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification |
DVCON 2014 – Panel on Mixed Signal Verification: what’s next ?
For Mixed-Signal afficionados or wannabes attending DVCON, I will be moderating next Monday a panel session on Mixed-signal verification (not on French wine making yet, sorry 🙂 ) . This event is sponsored by Accellera and more information can be found at:
Posted in AMS EDA tools, Mixed Signal/Cosimulation, verification |
