Analog Simulation Insights

Archive for the 'Mixed Signal/Cosimulation' Category

 

Musings on Mixed-signal Verification – Part 2

Abstraction models and use models in mixed-signal verification Hi folks! I am back! If you recall, in my previous post (Part 1), I outlined the key drivers behind the increasing need for mixed-signal verification today. In this post, I want to elaborate on the challenges and tradeoffs inherent in the different design abstraction models and verification use models that are prevalent today. First, what are design abstraction models and how do they differ? The answer lies in the level of design abstraction (cell-level, macro-level, block-level, full-chip or SoC-level), the type of design (analog, mixed-signal), how you choose to verify your design and what your verification objectives are. Abstraction models and verification use models usually go hand-in-hand. Traditionally, custom designs at the cell-level, macro-level, and block-level, are verified using what is known as the “Analog Top” or “SPICE Top” model. This model entails a bottom-up SPICE-centric verification approach wherein, the design is verified in SPICE netlist format using a SPICE testbench and a SPICE simulator (e.g., HSPICE). While this model ensures high verification accuracy, it is not scalable i.e., it cannot be extended to very large designs or full-chip verification, due to the performance/capacity limitations of SPICE simulators. But there are exceptions – discrete analog designs typically are verified using this model even at the full-chip level, but by using a FastSPICE simulator (e.g., CustomSim), and by incorporating limited behavioral modeling using System Verilog, Verilog, or Verilog-A, to alleviate the capacity constraints of the simulator. The figure below depicts such a scenario:

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Posted in AMS Circuits, analog, analog design, Behavioral Modeling, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized |

 

Musings on Mixed-signal Verification – Part 1

The increasing need for mixed-signal verification!

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Posted in AMS Circuits, analog, analog design, Behavioral Modeling, digital, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized |

 

DAC 2015 Synopsys Circuit Simulation Luncheon: Altera, ST, TSMC and Xilinx on Synopsys Industry Leading Performance for Analog Mixed-signal Designs

Improving the performance of existing technologies has always been a key element in the development of computational systems and EDA tools. However, as analog mixed-signal designs complexity drastically increases, conventional techniques are becoming outdated and new technologies must be adopted by designers.

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Posted in AMS EDA tools, EDA, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, verification |

 

VCS AMS at DVCON : Xilinx talk, demos, technical sessions and much more :)

Happy Friday,

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Posted in Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification |

 

Synopsys AMS SIG Event in Bangalore, India – ADI, ARM, ST and Xilinx present their latest solutions to resolve today analog mixed-signal challlenges

Happy new year everyone,

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Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification |

 

VCS AMS joint webinar with Synopsys, ST and ARM : latest insights on advanced mixed-signal verification

Happy Tuesday,

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Posted in AMS Assertions, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification |

 

DAC 2014 AMS panel videolog now available

We hosted a few weeks ago at DAC Synopsys AMS luncheon with speakers from Micronas, Infineon, AMD and ST.  The theme of this year’s event was “Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier”.

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Posted in AMS Circuits, AMS EDA tools, analog, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification |

 

DAC Synopsys AMS Technical Luncheon Panel – Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier

DAC is here and we are ready!

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Posted in AMS Circuits, AMS EDA tools, Mixed Signal/Cosimulation, Uncategorized, verification |

 

VCS AMS – Synopsys advanced mixed-signal verification solution to accelerate regression testing of mixed-signal SoCs

 You may have seen Synopsys recent announcement during SNUG:

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Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification |

 

DVCON 2014 – Panel on Mixed Signal Verification: what’s next ?

For Mixed-Signal afficionados or wannabes attending DVCON, I will be moderating next Monday a panel session on Mixed-signal verification (not on French wine making yet, sorry 🙂 ) . This event is sponsored by Accellera and more information can be found at:

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Posted in AMS EDA tools, Mixed Signal/Cosimulation, verification |