The increasing need for mixed-signal verification!
Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, semiconductor design is no longer confined to “semiconductor” companies. In the past few years, many electronics, communication, and computer equipment companies have brought ASIC and SoC design activities back in-house. They now consider these designs to be competitive differentiators and crucial intellectual property rather than commodities that should be outsourced. This is – in significant part – driven by an increase in mathematical algorithmic content being engineered into signal, image and video processing, and mixed-signal designs
Q&A: STE innovates their mixed-signal verification using CustomSim-VCS solution with real number modeling on AMS design
Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.
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As design complexity has continued to increase with the ongoing advances prescribed by Moore’s Law, it has become generally accepted that verification consumes more of a project’s time than the design itself. In forecasting (logic) designer productivity at future process nodes, the International Technology Roadmap For Semiconductors 2006 Update (ITRS) estimates that the average percentage of a project effort spent in verification is currently at 70%. Verification can mean many different things, but here I am primarily referring to functional verification.
Analog design is Black Magic??? Recently there have been two occurrences where this description of analog design has been used; a panel discussion at the IEEE SOC Conference in Taiwan (09/27/07), and Mike Santarini’s blog (09/18/07) at EDN Magazine.
Welcome to “Analog Insights”