Abstraction models and use models in mixed-signal verification Hi folks! I am back! If you recall, in my previous post (Part 1), I outlined the key drivers behind the increasing need for mixed-signal verification today. In this post, I want to elaborate on the challenges and tradeoffs inherent in the different design abstraction models and verification use models that are prevalent today. First, what are design abstraction models and how do they differ? The answer lies in the level of design abstraction (cell-level, macro-level, block-level, full-chip or SoC-level), the type of design (analog, mixed-signal), how you choose to verify your design and what your verification objectives are. Abstraction models and verification use models usually go hand-in-hand. Traditionally, custom designs at the cell-level, macro-level, and block-level, are verified using what is known as the “Analog Top” or “SPICE Top” model. This model entails a bottom-up SPICE-centric verification approach wherein, the design is verified in SPICE netlist format using a SPICE testbench and a SPICE simulator (e.g., HSPICE). While this model ensures high verification accuracy, it is not scalable i.e., it cannot be extended to very large designs or full-chip verification, due to the performance/capacity limitations of SPICE simulators. But there are exceptions – discrete analog designs typically are verified using this model even at the full-chip level, but by using a FastSPICE simulator (e.g., CustomSim), and by incorporating limited behavioral modeling using System Verilog, Verilog, or Verilog-A, to alleviate the capacity constraints of the simulator. The figure below depicts such a scenario:
The increasing need for mixed-signal verification!
Yes it is Thursday again 🙂
Blog post on Thursday, Happy hour on Friday… so I had to release it today:)
I know you all have been waiting for this blog to be back up 🙂
Well, because this blog is a technical blog, I thought it was a good time for a geek-friendly post :). Armed with my usual optimism and with the help of our in-house expert Dave Cronauer, I decided to give you a few tips to make your Verilog-AMS module more efficient. Dealing with customer issues for many years, one recurrent observation I had about behavioral models is that performance is strongly correlated with the quality of your module. Using a simpler model and changing some of your modeling techniques can bring you a significant speed up in term of simulations.
While at SNUG, I attended our AMS technical track session. One of the presentations described an innovative flow using UVM with Verilog-AMS. Synopsys CustomSim-VCS was successfully used on AMS designs to demonstrate the performance advantages of this methodology. The title was:
Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.
Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog, Analog and Custom Layout, analog design, Behavioral Modeling, Cell Characterization, Custom Designer, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Nanometer CMOS, Reliability, RF, Signal Integrity, SPICE, verification |