Analog Simulation Insights

Archive for the 'Analog and Custom Layout' Category


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Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog, Analog and Custom Layout, analog design, Behavioral Modeling, Cell Characterization, Custom Designer, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Nanometer CMOS, Reliability, RF, Signal Integrity, SPICE, verification


NanoTime Static Timing in Custom Designer

NanoTime is our transistor-level static timing product for custom designs. Since Custom Designer is for custom design too it was natural that we’d integrate the two tools together. Released in June of 2010, the NanoTime integration into Custom Designer lets users do concurrent timing and SI analysis for designs of up to 6 million devices and see the whole timing picture in schematics and layout.

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Posted in Analog and Custom Layout, Custom Designer, Nanometer CMOS


Focus on Layout Productivity – Part 1

Getting to the end-game faster in a chip design project is one of the driving forces for EDA. As EDA tools have matured over the years parts of the design flow have emerged as a major block of time. In custom design, the layout phase of blocks has become one area that needed serious attention. This phase often occupies as much 60 percent of the overall time for a given block and is an obvious target for productivity enhancers in a custom design tool.

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Posted in AMS EDA tools, analog, Analog and Custom Layout