Analog Simulation Insights

Archive for the 'SPICE' Category

 

Musings on Mixed-signal Verification – Part 2

Abstraction models and use models in mixed-signal verification Hi folks! I am back! If you recall, in my previous post (Part 1), I outlined the key drivers behind the increasing need for mixed-signal verification today. In this post, I want to elaborate on the challenges and tradeoffs inherent in the different design abstraction models and verification use models that are prevalent today. First, what are design abstraction models and how do they differ? The answer lies in the level of design abstraction (cell-level, macro-level, block-level, full-chip or SoC-level), the type of design (analog, mixed-signal), how you choose to verify your design and what your verification objectives are. Abstraction models and verification use models usually go hand-in-hand. Traditionally, custom designs at the cell-level, macro-level, and block-level, are verified using what is known as the “Analog Top” or “SPICE Top” model. This model entails a bottom-up SPICE-centric verification approach wherein, the design is verified in SPICE netlist format using a SPICE testbench and a SPICE simulator (e.g., HSPICE). While this model ensures high verification accuracy, it is not scalable i.e., it cannot be extended to very large designs or full-chip verification, due to the performance/capacity limitations of SPICE simulators. But there are exceptions – discrete analog designs typically are verified using this model even at the full-chip level, but by using a FastSPICE simulator (e.g., CustomSim), and by incorporating limited behavioral modeling using System Verilog, Verilog, or Verilog-A, to alleviate the capacity constraints of the simulator. The figure below depicts such a scenario:

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Posted in AMS Circuits, analog, analog design, Behavioral Modeling, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized |

 

SAE is Free!

Hello everyone,

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Posted in AMS Circuits, analog, analog design, Fast-SPICE, HSPICE, SPICE, verification |

 

Is Your MOSFET Suffering the Effects of Aging?

Hello everyone,

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Posted in analog, analog design, Device Modeling, digital, Fast-SPICE, HSPICE, Nanometer CMOS, Reliability, SPICE, verification |

 

Don’t Miss the HSPICE SIG Dinner in Santa Clara!

Happy Thursday!

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Posted in AMS Circuits, AMS EDA tools, analog design, HSPICE, Power integrity, Signal Integrity, SPICE |

 

DAC 2015 Synopsys Circuit Simulation Luncheon: Altera, ST, TSMC and Xilinx on Synopsys Industry Leading Performance for Analog Mixed-signal Designs

Improving the performance of existing technologies has always been a key element in the development of computational systems and EDA tools. However, as analog mixed-signal designs complexity drastically increases, conventional techniques are becoming outdated and new technologies must be adopted by designers.

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Posted in AMS EDA tools, EDA, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, verification |

 

Synopsys AMS SIG Event in Bangalore, India – ADI, ARM, ST and Xilinx present their latest solutions to resolve today analog mixed-signal challlenges

Happy new year everyone,

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Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification |

 

DAC 2014 AMS panel videolog now available

We hosted a few weeks ago at DAC Synopsys AMS luncheon with speakers from Micronas, Infineon, AMD and ST.  The theme of this year’s event was “Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier”.

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Posted in AMS Circuits, AMS EDA tools, analog, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification |

 

Synopsys/Zuken at DesignCon- Unique DDR capabilities using WaveView and HSPICE

You may be tired of hearing only about Mixed-signal verification, so why don’t we switch to signal Integrity? :). Looking at the recent announcements at CES and Intel’s expected release of server solutions using DDR4 memory later this year, I wanted to further explore this topic. We had a little time ago a very successful webinar that showed in more details DDR capabilities that SI users have and are currently adopting using a combined Synopsys- Zuken flow. Because of our customer testimonies and their enthusiasm on those capabilities, I therefore asked the owners (Griff, Hany) to demo this flow at DesignCon at the ChipHead theatre (see link below) and to talk to us a little more. Our Synopsys WaveView expert Manu V. Pillai is joining the discussion as well to provide more insights on WaveView, which is used by this flow.

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Posted in AMS Circuits, analog, analog design, Signal Integrity, SPICE, Uncategorized |

 

DAC 2013 AMS Verification event videolog

 Well after a couple of busy weeks traveling (and I am sure you really care about knowing this :)), I finally found some time to blog about our DAC AMS event held in Austin early June. We had a very successful event with some great technical presentations (hey that’s the feedback I received from the crowd..) from Micron, Broadcom, ST-Ericsson E, ARM and ST-Microelectronics. The topics ranged from low power and reliability and mixed signal verification and advanced memory characterization.

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Posted in AMS Circuits, AMS EDA tools, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Reliability, SPICE, verification |

 

DesignCon Panel on Behavioral modeling summary report- you have all been waiting for it :)

Blog post on Thursday, Happy hour on Friday… so I had to release it today:)

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Posted in AMS EDA tools, analog, analog design, Behavioral Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, RF, SPICE, Uncategorized |