Happy Thursday ! I can’t believe it is already end of July…
Well after a couple of busy weeks traveling (and I am sure you really care about knowing this :)), I finally found some time to blog about our DAC AMS event held in Austin early June. We had a very successful event with some great technical presentations (hey that’s the feedback I received from the crowd..) from Micron, Broadcom, ST-Ericsson E, ARM and ST-Microelectronics. The topics ranged from low power and reliability and mixed signal verification and advanced memory characterization.
Synopsys Invited FinFET talk at WMED: Q&A on FinFET variability and its impact on digital and analog circuits
If you have been following my blog, you may have noticed a couple of posts on FinFET technology, mostly on the modeling side. I recently worked with the WMED committee to look at innovative subjects (especially for those spots after lunch time :)). One topic we selected was the challenges faced by analog and digital designers when using a FinFET based process.
Attractive title, isn’t it? 🙂 I wanted to share with you some benchmarks we conducted with key partners using Discovery-AMS multi-core technology. This feature is available in 2013.3 release for Mixed Signal Verification and allows you to considerably speed up your simulation. Two key advantages of Discovery-AMS are performance and versatility. By combining the efficiency of a Fast-Spice solver with multithreading, we were able to boost performance up to 10X.
Yes it is Thursday again 🙂
Blog post on Thursday, Happy hour on Friday… so I had to release it today:)
AMD talks about advanced regression and verification for Mixed-Signal Designs using CustomExplorerUltra
If you read my blog or other EDA related blogs, you probably have already figured out that verification, specifically for mixed-signal designs, is getting increasingly complex. Different variables have to be taken in consideration: complexity of your design environment or topology, high-volume of regression runs, simulation speed are just a few of those . The verification methodology has also to support multiple languages, and work with different netlist formats available across the industry. As such, there is a crucial need for an integrated mixed-signal verification environment that focuses on functionality, reliability, and performance.
Q&A: STE innovates their mixed-signal verification using CustomSim-VCS solution with real number modeling on AMS design
Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.
As a chair(wo)man for the AMS track at DesignCon (yes I know, you heard it before 🙂 ), I just want to inform you that the call for abstracts is now open for DesignCon 2013:
Q&A with ST-Ericsson: Latest ERC flow innovations using CustomSim CCK for optimal verification coverage
Circuit design implementation has become increasingly complex in deep submicron technologies. Multiple processor cores, I/Os peripherals, complex analog circuits, and logic are now being implemented onto the same chip. Ensuring product reliability to meet design goals and to achieve good yield has become a crucial step in today design cycle. With complex IP, system integration, and multiple power domains, you need an extremely flexible and powerful EDA solution to tackle those circuit verification demands.