Analog Simulation Insights

Archive for the 'analog design' Category

 

Q&A: STE innovates their mixed-signal verification using CustomSim-VCS solution with real number modeling on AMS design

Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.

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Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog design, digital, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification

 

Q&A with ST-Ericsson: Latest ERC flow innovations using CustomSim CCK for optimal verification coverage

Circuit design implementation has become increasingly complex in deep submicron technologies. Multiple processor cores, I/Os peripherals, complex analog circuits, and logic are now being implemented onto the same chip. Ensuring product reliability to meet design goals and to achieve good yield has become a crucial step in today design cycle. With complex IP, system integration, and multiple power domains, you need an extremely flexible and powerful EDA solution to tackle those circuit verification demands.

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Posted in AMS Circuits, AMS EDA tools, analog design, EDA, Fast-SPICE, Reliability, verification

 

UVM-based random verification using CustomSim-VCS for Analog Mixed Signal Designs

While at SNUG, I attended our AMS technical track session. One of the presentations described an innovative flow using UVM with Verilog-AMS. Synopsys CustomSim-VCS was successfully used on AMS designs to demonstrate the performance advantages of this methodology. The title was:

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Posted in AMS Circuits, analog design, Behavioral Modeling, Fast-SPICE, Uncategorized, verification

 

10 tips to improve performance using HSPICE

Good morning ! well, since this is a technical blog, I thought I owed you some tools-related posts 🙂 I am compiling below 10 tips to make your HSPICE simulation even more efficient 🙂

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Posted in analog, analog design, SPICE, Uncategorized

 

Back from DesignCon !

Well, I have to say DesignCon 2012 was a complete success. Attendance was high and many industry topics were covered.

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Posted in AMS Circuits, analog, analog design, Behavioral Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Signal Integrity, SPICE

 

Welcome Again!

Hello!

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Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog, Analog and Custom Layout, analog design, Behavioral Modeling, Cell Characterization, Custom Designer, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Nanometer CMOS, Reliability, RF, Signal Integrity, SPICE, verification

 

Sweet!

I was recently at an offsite where CAD engineers, Designers, and Custom Designer developers were all present. We were reviewing capabilities and deployments of Custom Designer in our IP business. One of the CAD engineers was reviewing some capabilities they had implemented using Hercules manipulation of GDS that allowed analog designers to better “see” their designs and optimize the layout.

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Posted in AMS EDA tools, analog, analog design

 

The Heart of the Problem

Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.

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Posted in AMS EDA tools, analog, analog design, EDA, Fast-SPICE, SPICE, verification

 

Parallels

High accuracy analog simulations face the classic problem of scalability. Doubling the size of a design roughly quadruples the size of the matrix and dramatically increases a simulation’s run time to the point where a design team simply cannot wait for it to finish. Conversely, the team cannot proceed without knowing that the design is functioning. Conundrum!

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Posted in AMS Circuits, analog, analog design, EDA, SPICE, verification

 

Only Three Months to Get There

For those of you who made it to the recent San Jose SNUG meeting, you may have noticed a presentation titled, “Using Custom Designer to ‘Blow Up’ a Design”. I can assure you there were no pyrotechnics involved – the ‘Blow Up” really meant ‘Scale Up” since the paper detailed how we were able to use the power of Custom Designer to reverse the sands of time.  Our normal IP flow is a forward migration from an existing process node down the scaling curve to a more advanced – smaller – node.  In this case, several customers requested a 130nm implementation of a piece of our production proven IP that had just been released on 65nm. Our customer made this request for a variety of reasons but one key reason was tied to the higher cost of 65nm mask production. Moving the design to 130nm would save them a ton of money even if it seems to be moving backwards.

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Posted in AMS Circuits, AMS EDA tools, analog, analog design, Custom Designer, EDA, Fast-SPICE, Nanometer CMOS, SPICE