Abstraction models and use models in mixed-signal verification Hi folks! I am back! If you recall, in my previous post (Part 1), I outlined the key drivers behind the increasing need for mixed-signal verification today. In this post, I want to elaborate on the challenges and tradeoffs inherent in the different design abstraction models and verification use models that are prevalent today. First, what are design abstraction models and how do they differ? The answer lies in the level of design abstraction (cell-level, macro-level, block-level, full-chip or SoC-level), the type of design (analog, mixed-signal), how you choose to verify your design and what your verification objectives are. Abstraction models and verification use models usually go hand-in-hand. Traditionally, custom designs at the cell-level, macro-level, and block-level, are verified using what is known as the “Analog Top” or “SPICE Top” model. This model entails a bottom-up SPICE-centric verification approach wherein, the design is verified in SPICE netlist format using a SPICE testbench and a SPICE simulator (e.g., HSPICE). While this model ensures high verification accuracy, it is not scalable i.e., it cannot be extended to very large designs or full-chip verification, due to the performance/capacity limitations of SPICE simulators. But there are exceptions – discrete analog designs typically are verified using this model even at the full-chip level, but by using a FastSPICE simulator (e.g., CustomSim), and by incorporating limited behavioral modeling using System Verilog, Verilog, or Verilog-A, to alleviate the capacity constraints of the simulator. The figure below depicts such a scenario:
The increasing need for mixed-signal verification!
AMS HSPICE SIG dinner during DesignCon 2015: Best-in-class techniques and solutions for Power and Signal Integrity analysis
You may be tired of hearing only about Mixed-signal verification, so why don’t we switch to signal Integrity? :). Looking at the recent announcements at CES and Intel’s expected release of server solutions using DDR4 memory later this year, I wanted to further explore this topic. We had a little time ago a very successful webinar that showed in more details DDR capabilities that SI users have and are currently adopting using a combined Synopsys- Zuken flow. Because of our customer testimonies and their enthusiasm on those capabilities, I therefore asked the owners (Griff, Hany) to demo this flow at DesignCon at the ChipHead theatre (see link below) and to talk to us a little more. Our Synopsys WaveView expert Manu V. Pillai is joining the discussion as well to provide more insights on WaveView, which is used by this flow.
As DesignCon conference approaches and as the chairman of the AMS track, I would like to inform you on a few technical events happening there. In addition to our AMS track, we have added several events:
Synopsys Invited FinFET talk at WMED: Q&A on FinFET variability and its impact on digital and analog circuits
If you have been following my blog, you may have noticed a couple of posts on FinFET technology, mostly on the modeling side. I recently worked with the WMED committee to look at innovative subjects (especially for those spots after lunch time :)). One topic we selected was the challenges faced by analog and digital designers when using a FinFET based process.
Blog post on Thursday, Happy hour on Friday… so I had to release it today:)