Analog Simulation Insights

Archive for the 'AMS Assertions' Category

 

VCS AMS joint webinar with Synopsys, ST and ARM : latest insights on advanced mixed-signal verification

Happy Tuesday,

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Posted in AMS Assertions, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification |

 

DAC 2013 AMS Verification Luncheon: Advance Your Mixed-signal Verification Techniques to the Next Level

 

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Posted in AMS Assertions, AMS EDA tools, Mixed Signal/Cosimulation, Reliability, verification |

 

MTV 2012 Mixed Signal Verification Panel – Can Mixed Signal verification be done with no analog solver ?

Well, it has been a while, hasn’t it? No, I have not been lazy, I have just been busy working on Synopsys amazing portfolio of simulators. 🙂

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Posted in AMS Assertions, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, verification |

 

Q&A: STE innovates their mixed-signal verification using CustomSim-VCS solution with real number modeling on AMS design

Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.

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Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog design, digital, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification |

 

Welcome Again!

Hello!

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Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog, Analog and Custom Layout, analog design, Behavioral Modeling, Cell Characterization, Custom Designer, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Nanometer CMOS, Reliability, RF, Signal Integrity, SPICE, verification |

 

Using a blog to develop your personal brand

If you are reading this, you may have had thoughts on blogging yourself, or perhaps you already are a blogger. One of the most valuable lessons that I have learned from writing a blog is how it can be be used for creating and publicizing my personal “brand”. Personal branding is a way to demonstrate the unique expertise and value that you can provide, to potential employers as well as to colleagues in your profession.

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Posted in AMS Assertions, AMS EDA tools, analog, analog design, Analog synthesis, digital, EDA, Fast-SPICE, SPICE, verification |

 

Square pegs and round holes

Hi All,

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Posted in AMS Assertions |

 

Accellera Discussions on AMS Assertions

The Verilog-AMS Technical Subcommittee of Accellera held another in a series of conference call discussions on Tuesday Oct-7, to further explore the topic of AMS Assertions. The meeting began with a review of some work that was published at the workshop on Formal Verification of Analog Circuits, which I wrote about here in June.

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Posted in AMS Assertions |

 

continuing the discussion… Taxonomy of Analog Properties

Great comments from Jonathan on yesterday’s post, so I will continue the discussion here as a new post so that RSS readers get the latest. Jonathan, thanks again for contributing to the discussion.

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Posted in AMS Assertions |

 

Taxonomy of analog properties.

Sorry.. that “big word” just slipped out here. Let me explain.

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Posted in AMS Assertions |