Analog Simulation Insights

 

AMS SIG India, 2017 – Update

Happy Wednesday folks!

If you recall, AMS SIG India was held in Bengaluru last month (2/16/17). It was well attended and quite successful! Distinguished speakers from Samsung, Xilinx, Qualcomm, STMicroelectronics, and Synopsys R&D, spoke on a wide variety of topics centered around the use of Synopsys solutions to address AMS custom design and verification challenges for FinFETs.

The event keynote was delivered by Parvinder Rana, Director Library Group, Samsung SLSI. The keynote focused on foundation IP design challenges in advanced planar and FinFET nodes.

I had a chance to sit down with Parvinder after the event. Here is a transcript of that conversation:


Anand: Hello Parvinder! Thanks for taking the time to talk to us…

Parvinder: Hi Anand! Thanks for having me…

Anand: First of all, tell me about your experience delivering the keynote…

Parvinder: Delivering the keynote gave me a good opportunity to put my perspective in front of the AMS design community in Bangalore. “Advanced nodes” is a very interesting topic as it is tied to the future of the industry and also because there are so many different factors involved, which makes it difficult to paint a clear picture of where the industry is headed. It was also a good opportunity for me to create awareness about Samsung India’s hardware development efforts since Samsung India is primarily known for software development. The process of putting the presentation together took some effort since I had to be very careful about the data points I pick. I had a bit of apprehension about how the presentation would be received since the content was very technical…

Anand: But, going by how engaged the audience was, I would say the presentation was well received…

Parvinder: Oh yes! I was both relieved and happy to see the response from the audience. I thought the questions were very thoughtful and relevant…

Anand: What was your overall impression of AMS SIG? What were your impressions about the various technical presentations?

Parvinder: I thought the event was very well organized. The presentations were very relevant for the industry today. The diversity of the audience across different orgs, domains (layout, char, design, different type of IPs) was good. But, I felt participation from the core design community could have been higher.

Regarding the presentations, let me go down the list:

  1. The Qualcomm presentation (“Characterizing Multi-bit Flip-Flops with SiliconSmart”) was very relevant to me since it focused on run time optimization of multi bit flops, which impacts characterization turnaround time (TAT) and thus, overall development costs.

 

  1. The Xilinx presentation (“Advanced DDR4 PHY DQ-DQS Calibration Verification Using VCS AMS Monte Carlo Variation”) which focused on performing Monte Carlo analysis in the context of mixed-mode simulations, was very good. This was the first time I saw statistical analysis being used in mixed-mode analysis. In DDR type applications, this can add a lot of value because it helps “close the loop” between the various components of the DDR system. I think many interface IP designers will find this very useful.

 

  1. The STMicroelectronics presentation (“Reducing Memory Compiler Development Time Using Custom Compiler”) highlighted the use of Synopsys’ Custom Compiler to improve layout productivity. I think the emphasis on features such as In-design parasitic estimation and EM-driven layout was very useful, since they are very relevant in current and emerging technologies and in my opinion are critical to driving down development lead time.

Anand: Thanks for the summary. So is it fair to say then that these presentations were in-line with the trending/relevant topics of the day?

Parvinder: Yes. Definitely.

Anand: Parvinder, it was a pleasure talking to you. And thanks for the excellent keynote! We hope to have you back sometime again.


And I also want to give a shout-out to Synopsys R&D for an excellent keynote to cap off the event. The presentation highlighted the key AMS design challenges in FinFETs and articulated how Synopsys Custom Compiler and circuit simulation solutions such as HSPICE, FineSim, and CustomSim, can help address these challenges, be it the complex modeling requirements of the new FinFET device, the increased complexity in design and placement rules, or the increasing impact of device variation, aging, and reliability on design performance.

Finally, I want to leave with you with a few pics. from the event. Until next time…

1_dsc_11491_dsc_12141_dsc_1192

  • Print
  • Digg
  • del.icio.us
  • Facebook
  • Google Bookmarks
  • LinkedIn
  • RSS
  • Twitter