Posted by Anand Thiruvengadam on February 6, 2017
VCS AMS – The Synopsys solution for mixed-signal verification
I am back! If you recall, in my previous posts (Part 1 & Part 2), I outlined the key drivers behind the increasing need for mixed-signal verification and the challenges and tradeoffs inherent in the different design abstraction models and verification use models that are prevalent today. Today, I will highlight the Synopsys solution for mixed-signal verification – VCS AMS.
Before we do a deep-dive into VCS AMS, let’s do a quick recap on why we need mixed-signal simulators.
Case for mixed-signal simulators
Purely behavioral simulations based on models (e.g., Verilog, System Verilog) are computationally “very light” and therefore extremely fast. This performance comes at a price – the inability to simulate “transistor-level circuit behavior” and the associated loss in simulation accuracy. With the advent of techniques such as Real Number modeling, analog simulation behavior and accuracy have improved, but there still exists a gap between a behavioral model and true circuit behavior.
The best and only solution is to use a mixed-signal simulator, one that can support both digital (i.e., behavioral) simulations and SPICE simulations (for blocks requiring transistor-level accuracy). And with a capable mixed-signal simulator, one can extend digital regression techniques to mixed-signal simulations seamlessly.
So what is VCS AMS?
VCS AMS is a simulator that combines best-in-class solutions from the Digital and FastSPICE worlds -VCS and CustomSim – to provide a highly capable and differentiated mixed-signal verification solution.
Here is how VCS AMS is differentiated across the four requirement categories (as outlined in Part 1):
The performance in a mixed-signal simulator is primarily dependent on the SPICE/FastSPICE simulator due to the computational requirements associated with transistor-level simulations. This performance bottleneck is further exacerbated by large post-layout netlists. Therefore, it is imperative that the mixed-signal simulator incorporate a high-capacity/high-performance FastSPICE simulator. VCS AMS incorporates a best-in-class FastSPICE engine – CustomSim – to enable class-leading mixed-signal simulation performance.
And the two tools – VCS and CustomSim – are integrated at the kernel-level through Direct Kernel Integration (DKI), rather than through APIs, to ensure higher performance and support for continuous tool innovation. The end-result is a solution that enables mixed-signal regression with transistor-level accuracy.
Additionally, VCS AMS supports multi-core scaling to enable users to derive additional performance gains by running the simulation across multiple cores (e.g., 4 cores vs. 1 core). This is a win-win for the user because of the simultaneous improvement in performance and hardware utilization efficiency.
As articulated earlier, today’s complex mixed-mode designs span the entire design abstraction, verification use model, and modeling language spectrum. This is driven by the varying maturity levels of mixed-signal verification environments, which in turn is dependent on the CAD infrastructure, and user knowledge and preferences. Therefore, meeting these varied and complex requirements, is key to the efficacy of any mixed-signal solution. Additionally, these requirements can co-exist for the same top level design, necessitating the need for a single solution that can address all of them.
With broad support for various abstraction and use models and multiple modeling languages/approaches, including System Verilog Nettypes, VCS AMS helps strike a good balance between performance and accuracy.
“Re-use” is one of the perennial themes of productivity improvement solutions. In the context of mixed-signal verification, the ability to re-use a digital testbench, with all the assertions and checkers, is critical to improving productivity. VCS AMS ensures a seamless transition from digital verification to mixed-signal verification by not only supporting testbench re-use, but also through automatic insertion of A/D and D/A interface elements and automatic real-to-electrical and electrical-to-real net mapping. Additionally, the user can extend advanced UVM techniques to mixed-signal verification, thus greatly enhancing verification efficacy and coverage.
Another key driver of productivity is efficient simulation management, which includes simulation setup, job management, visualization, and debug. VCS AMS provides robust debug and simulation management capabilities, through integration with the broader Synopsys solution ecosystem. Users can use Verdi for comprehensive simulation visualization and debug in digital-centric use models, and the native Simulation and Analysis Environment (SAE) in CustomSim for simulation setup, visualization, and debug in analog-centric use models.
What differentiates a mixed-signal simulator is its support for advanced analysis capabilities that can help extend the boundaries of traditional mixed-signal verification. Case in point – Monte Carlo analysis in a mixed-signal context. VCS AMS supports not only Monte Carlo analysis, but also other features such as Unified Power Format (UPF) for power-aware verification, design and electrical rule checks, parametric checks, Safe Operating Area (SOA) checks, cross-talk analysis, and leakage detection checks.
In summary, the Synopsys solution VCS AMS, combines two best-in-class solutions – VCS and CustomSim – to provide a highly capable and differentiated mixed-signal verification solution.
I hope you have found this 3-part series useful and informative.
For additional information on VCS AMS, please see below –
Product Information – https://www.synopsys.com/verification/ams-verification/vcs-ams.html
VCS AMS @ DAC (Videos) – https://www.synopsys.com/verification/resources/videos.html
In the next few posts, I will talk more about the SIG events – the recently concluded HSPICE SIG and the upcoming AMS SIG event
So please stay tuned…