Analog Simulation Insights


Musings on Mixed-signal Verification – Part 2

Abstraction models and use models in mixed-signal verification
Hi folks!
I am back! If you recall, in my previous post (Part 1), I outlined the key drivers behind the increasing need for mixed-signal verification today. In this post, I want to elaborate on the challenges and tradeoffs inherent in the different design abstraction models and verification use models that are prevalent today.
First, what are design abstraction models and how do they differ?
The answer lies in the level of design abstraction (cell-level, macro-level, block-level, full-chip or SoC-level), the type of design (analog, mixed-signal), how you choose to verify your design and what your verification objectives are. Abstraction models and verification use models usually go hand-in-hand. Traditionally, custom designs at the cell-level, macro-level, and block-level, are verified using what is known as the “Analog Top” or “SPICE Top” model. This model entails a bottom-up SPICE-centric verification approach wherein, the design is verified in SPICE netlist format using a SPICE testbench and a SPICE simulator (e.g., HSPICE).
While this model ensures high verification accuracy, it is not scalable i.e., it cannot be extended to very large designs or full-chip verification, due to the performance/capacity limitations of SPICE simulators. But there are exceptions – discrete analog designs typically are verified using this model even at the full-chip level, but by using a FastSPICE simulator (e.g., CustomSim), and by incorporating limited behavioral modeling using System Verilog, Verilog, or Verilog-A, to alleviate the capacity constraints of the simulator. The figure below depicts such a scenario:


As we move towards full-chip and/or SoC-level verification, the more logical (and certainly more popular) choice is the “Digital Top” model which is based on a digital-centric verification methodology. This model entails the use of a digital top-level testbench (e.g., Verilog, System Verilog) to verify what is mostly either a digital netlist (only behavioral models) or a hybrid netlist (behavioral and SPICE), using either a digital simulator (e.g., VCS) or a mixed-signal simulator (e.g., VCS AMS). This model suits both top-down and bottom-up verification approaches.
By virtue of the digital-centric approach, the model is scalable and it provides for excellent coverage and high performance. But the model is limited to connectivity and high-level functional verification and cannot be extended to design performance (e.g., Power, Leakage, Noise) verification. The figure below depicts such a model:



What about verification use models?
The different design abstraction models are naturally aligned to certain verification models or approaches, but the delineation typically is around the size of the design that is being verified. For example, in the traditional “Analog Top” model, for the lower levels of abstraction (e.g., cell-/macro-level), the “All SPICE” verification model is most commonly used. This model entails the use of a SPICE or FastSPICE simulator to verify the design in SPICE netlist format.

As we progress higher in the design abstraction (e.g., block-level, full-chip or SoC-level), the “All Digital” model comes into play due to its digital-centric verification approach, wherein, a digital simulator (e.g., VCS) is used to simulate a digital netlist consisting of behavioral models (e.g., System Verilog, Verilog, Verilog-A). And then you have the “Mixed-signal” verification model that entails the use of a mixed-signal simulator such as VCS AMS (VCS + CustomSim) to verify both digital and hybrid netlists and thus is applicable to macro-/block-/full-chip or SoC-level netlists. The inherent tradeoffs are obvious:

The “All Digital” model is ideally suited to run digital regressions enabling extensive and sophisticated coverage at high performance levels. But it is not suited for design performance (e.g., Power, Noise) verification. The “All SPICE” model is suited for highly accurate verification, including design performance verification, but is limited in coverage and is not scalable due to its SPICE-centric approach.

The “Mixed-signal” model combines the “best of both worlds” to provide a solution that enables digital regression, extensive coverage, and accuracy for large designs at high performance levels.
The figure below captures the various use models and the inherent tradeoffs:



In my next post, I will touch upon the key highlights of VCS AMS – the Synopsys solution for mixed-signal verification.
Until then…