The increasing need for mixed-signal verification!
Happy new year folks!
I hope the new year is productive (work-wise) for everyone. As I look back at 2016, it is hard to believe that I have logged 4 months already in my current role at Synopsys. If you recall, my first blog was back in Oct’16. In these four months, I have come to appreciate the incredible effort that goes in to creating the different Synopsys AMS tools out there in the market today. One such tool that is on my mind today is VCS AMS – the Synopsys solution for mixed-signal verification.
Why VCS AMS? Well, in the past few months, I have been repeatedly asked by various customers the following question – how do I ensure that my large mixed-signal design, with interdependent analog and digital blocks, is bug free? And I have always pitched VCS AMS as the answer to that question.
As you know mixed-signal verification is becoming increasingly important because today’s designs are large, complex, and truly mixed-mode (i.e., contain interdependent analog and digital blocks). And the need for mixed-signal verification transcends functional and design abstraction boundaries, I.e., you need mixed-signal verification irrespective of whether you have an analog-centric design or a digital centric design.
So I wanted to use this forum to share relevant and appropriate aspects of the various conversations I have had with my customers regarding mixed-signal verification needs, challenges, and solutions. I will share these thoughts via a 3-part series. In the first part, I will outline why there is an increasing need for mixed-signal verification. In the second part, I will elaborate on the challenges and tradeoffs inherent in the different design abstraction models and verification use models that are prevalent today. Finally, in the third part, I will highlight how the Synopsys solution – VCS AMS, can help address these challenges.
So why is there an increasing need for mixed-signal verification?
There are three primary drivers today:
Driver # 1 – Transition to advanced technology nodes
As we transition to more advanced technology nodes, the design complexity increases exponentially. And so does the cost of design and manufacturing, rendering silicon bugs, ECOs, and design iterations extremely expensive! For example, IC design costs jump by 100% as you transition from 20nm to 16/14nm (Source: IBS Nov 2015). This trend continues for more advanced FinFET nodes. Fuse trimming, register programming and mask spins are no longer economical. And increasingly, they are not adequate to cover all the eventualities either.
So there is a real need for early detection of design issues and anomalies!
Driver # 2 – Increasing functional integration in ICs resulting in larger and more complex mixed-mode designs
Growth in segments such as Mobile and Consumer, is driving the need for highly integrated embedded SoCs. For example, it is estimated that by 2020, 90% of Mobile SoCs will feature integrated baseband (Source: The McClean Report, IC Market Drivers – IC Insights 2016).
This increase in functional integration will drive up design complexity, and will result in larger mixed-mode designs with more digitally-assisted analog, thus requiring greater performance and functional verification. Highly integrated SoCs also means multiple digital and analog/mixed-signal blocks co-existing on the same die, thus requiring support for different abstraction models (e.g., Analog Top, Digital Top), verification use models (All SPICE mode, All Digital, Mixed-signal), and modeling languages.
Thus, there is a need for a robust and flexible mixed-signal verification solution that can support multiple abstraction models and verification use models!
Driver # 3 – Need for higher performing and more reliable ICs, driven by key market segments
Segments such as Automotive and Networking are pushing the envelope in terms of performance and reliability. For example, wireless throughput is expected to see a 10X increase as we transition to emerging standards such as WiGig. And automotive ICs are now expected to have 3X longer operating lifetime (Source: The McClean Report, IC Market Drivers – IC Insights 2016).
The increase in performance and reliability requirements in ICs translates to a need for more rigorous characterization including mixed-signal characterization that can be performed seamlessly across design hierarchies and mixed-mode design boundaries. For example, performing power-aware and power-intent verification across mixed-mode design boundaries using flows such as UPF, is critical to meeting power-up/power-down and low power specifications. Similarly, assessing the impact of random variation using Monte Carlo analysis across mixed-mode design boundaries is key to ensuring overall design reliability and robustness.
Thus, there is a need for a highly capable mixed-signal verification solution that supports advanced analyses!
In summary, the key mixed-signal verification requirements can be categorized across these 4 main themes – Performance, Flexibility, Productivity, and Advanced Analyses – as shown in the figure below:
In my next post, I will elaborate on the tradeoffs inherent in the various abstraction models (e.g., “Digital Top”, “Analog Top”) and verification use models (e.g., “All Digital”, “Mixed-signal”, “All SPICE”). After that, I will talk about VCS AMS and highlight some of its key capabilities.