As promised, I wanted to report on the recently concluded Austin SNUG event. It was conducted at the Hilton Grand in downtown Austin on Sep’29th.
Check out the SNUG Austin link – http://www.synopsys.com/Community/SNUG/Austin/Pages/default.aspx – for more details on the event.
Event at a Glance
The Synopsys keynote – “Innovation in the Age of Smart Everything” – was delivered by Deidre Hanford, EVP, Customer Engagement
The event proceedings contained a healthy mix of user paper presentations and Synopsys tutorials across the 6 different tracks, as seen below on the charts:
The AMS focused track – Full Custom Implementation – had two user paper presentations and two Synopsys tutorials.
- Statistical Characterization Methodology to Design and Margin for 16nm FinFET Flops by NXP: The paper describes the benefits of using Liberty Variation Format (LVF) characterization to account for timing uncertainty and errors arising out of transistor On-chip variation (OCV). LVF characterization accounts for various factors impacting timing variation including timing arc, states, and topology. The paper also highlights the use of Synopsys SiliconSmart to not only implement sensitivity-based LVF characterization but also deliver significant reduction in characterization time by leveraging several in-built knobs.
- Power-Intent Verification Methodology in Multi-Voltage Domain Custom Memory Macro to Prevent Circuit Failures by AMD: This paper describes the use of Synopsys ESP-CV to perform Power-intent Verification (PIV). PIV helps enable power integrity checks and helps detect issues such as incorrect or missing level-shifters, sneak paths, and high leakage paths across multiple voltage domains.
- Custom Compiler Technology Walk-through: A very cool demo that gives you a look “under the hood” of Custom Compiler – the new custom design environment solution from Synopsys. Custom Compiler is specifically targeted towards FinFET designs delivering significant productivity improvements for circuit and mask designers. Custom Compiler features a full feature schematic editor, visually assisted layout automation, an integrated simulation environment, and OpenAccess compatibility enabling complex FinFET layouts to be completed in hours vs. days.
- Walk-through of SAE – The New Simulation Analysis Environment in the Latest Release of HSPICE, FineSim, and CustomSim: A demo on SAE, the new comprehensive simulation environment solution from Synopsys. SAE is native to all three simulators – HSPICE, FineSim, and CustomSim (XA). SAE offers a robust GUI with access to the latest simulator features, and advanced data mining and charting, thus removing the need for third-party simulation environment solutions.
Pulse of the Audience
The audience was very diverse consisting of users i.e., customers, and Synopsys employees – hosts, presenters, and volunteers. The AMS track paper presentations and tutorials were well received, as is evident from the audience survey scores (scale of 1 to 7):
In case you are interested in reviewing the papers/tutorials, you may download them from – http://www.synopsys.com/community/snug/pages/proceedingLp.aspx?loc=Austin&locy=2016
The SNUG event is a great forum for partners and customers (users) to showcase how they leveraged Synopsys solutions to address some of their most challenging design verification problems. And it serves to educate not just users, but Synopsys as well.
Our next SNUG event is the big one – SNUG Silicon Valley – slated for Mar’2017 – https://www.synopsys.com/Community/SNUG/Silicon%20Valley/pages/default.aspx. I encourage all AMS designers and CAD gurus to attend this event.
Until next time..