SNUG Austin 2016
Hey there!
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Synopsys AMS technical luncheon at DAC 2016: Robust AMS Design Verification by Samsung, Oracle, ST and Qualcomm
Time of the year again 🙂
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HSPICE Insider Insights: Gain and Noise Prediction
Hello again HSPICE users!
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MOS Reliability Analysis Webisode (Part 2)
Hello again HSPICE users!
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Improve Analog Verification Productivity Using SAE
For those of you who would like more information about Synopsys’ Simulation and Analysis Environment (SAE), we are hosting a webinar showcasing SAE and how you can use its unique features to improve your productivity. The webinar premieres Feb. 17 at 10:00 a.m. PST and will be available on-demand thereafter). I have asked Deepa Kannan, who is hosting this webinar, to give us more insights.
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HSPICE Celebrates 35 Years of Gold-standard Success
Hello again, HSPICE aficionados! (You may have noticed a trend—the HSPICE folks have been very busy lately!)
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SAE is Free!
Hello everyone,
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Is Your MOSFET Suffering the Effects of Aging?
Hello everyone,
Posted in analog, analog design, Device Modeling, digital, Fast-SPICE, HSPICE, Nanometer CMOS, Reliability, SPICE, verification | Comments Off on Is Your MOSFET Suffering the Effects of Aging?
Don’t Miss the HSPICE SIG Dinner in Santa Clara!
Happy Thursday!
Posted in AMS Circuits, AMS EDA tools, analog design, HSPICE, Power integrity, Signal Integrity, SPICE | Comments Off on Don’t Miss the HSPICE SIG Dinner in Santa Clara!
