Posted by Hélène Thibiéroz on May 27, 2015
Improving the performance of existing technologies has always been a key element in the development of computational systems and EDA tools. However, as analog mixed-signal designs complexity drastically increases, conventional techniques are becoming outdated and new technologies must be adopted by designers.
As such, we wanted the focus of this year’s event to be performance, highlighting through customer presentations how Synopsys circuit simulation tools’ superior performance allows analog/mixed-signal circuit designers to address the challenges of today and tomorrow.
During this lunch event, Altera, STMicrolectronics, TSMC and Xilinx will present their experiences using leading performance techniques recently implemented in Synopsys’ AMS simulators. These experts will share their successes in boosting performance and bringing their methodologies to the next level from SRAM to Memory and FPGA for advanced process nodes.
This event will be held on Monday, June 8, 2015 from 11:30 a.m to 1:30 p.m. at the Park Central Hotel (formerly Westin), Metropolitan Ballroom III.
Attendance at this event is free, but registration is required. And in addition to a delectable lunch, attendees will be entered into a drawing to win a GoPro HERO4 Silver camera 🙂
You can learn more about this event and register at:
As far as performance in the context of advanced nodes layout and design, you also may want to attend Synopsys Custom Design Luncheon, where key customers would present how adopting Synopsys Custom Design Tools enabled them to speed advanced-node layout .
For more information and to register, you can use the link below:
Looking forward to seeing you there !