Greetings,
Posted in Uncategorized | Comments Off on Q&A with Altera: How to improve your advanced-node design productivity using Synopsys SPICE Simulation and Analysis environment
Happy pre-Turkey D-2 day !
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Hello all,
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Greetings,
Posted in Uncategorized | Comments Off on DAC 2015 Circuit Simulation Videolog now available
Improving the performance of existing technologies has always been a key element in the development of computational systems and EDA tools. However, as analog mixed-signal designs complexity drastically increases, conventional techniques are becoming outdated and new technologies must be adopted by designers.
Posted in AMS EDA tools, EDA, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, verification | Comments Off on DAC 2015 Synopsys Circuit Simulation Luncheon: Altera, ST, TSMC and Xilinx on Synopsys Industry Leading Performance for Analog Mixed-signal Designs
Happy Friday,
Posted in Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | Comments Off on VCS AMS at DVCON : Xilinx talk, demos, technical sessions and much more :)
Happy Thursday,
Posted in AMS Circuits, AMS EDA tools, analog design, Signal Integrity | Comments Off on AMS HSPICE SIG dinner during DesignCon 2015: Best-in-class techniques and solutions for Power and Signal Integrity analysis
Happy new year everyone,
Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification | Comments Off on Synopsys AMS SIG Event in Bangalore, India – ADI, ARM, ST and Xilinx present their latest solutions to resolve today analog mixed-signal challlenges
