Analog Simulation Insights

 

DVCON Europe: Extending Proven Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS

Greetings !

VCS AMS is doing really well. After a successful webinar with ST and ARM and the release of a white paper,  we are continuing our momentum with a tutorial at DVCON Europe on Tuesday, October 14th:

http://dvcon-europe.org/presentation/tutorial-t14-extending-proven-verification-techniques/

This highly technical tutorial will presents how the VCS AMS mixed-signal verification solution provides superior performance and flexibility. It was developed around best-in-class methodologies to extend proven digital verification techniques into mixed-signal designs. VCS AMS encompasses, but is not restricted to, capabilities for time efficient simulations using “Save and Restore” technology, aligned with the SV1800 industry standard syntax for “SystemVerilog nettype” constructs, represented as a holistic methodology within AMS Testbench that is underpinned by extremely successful UVM library.

DVCON 2014 VCS AMS Tutorial

The breadth and depth of usage of the individual portions within the solution are explained by real user case studies: extensive usage of VCS AMS Save and Restore for boosting productivity by STMicroelectronics and performance-driven VCS AMS behavioral modeling flow by Micronas.

So yes, you will miss Octoberfest but you get to attend an amazing webinar 🙂

In addition, if you want to access our previous webinar and review VCS AMS white paper “Extending Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS”, I have listed the links below.

VCS AMS webinar

VCS AMS white paper

As usual, your feedback is more than welcome.

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