Analog Simulation Insights


HSPICE SIG, DesignCon, Busy month for Synopsys AMS

 As DesignCon conference approaches and as the chairman of the AMS track, I would like to inform you on a few technical events happening there. In addition to our AMS track, we have added several events:

  •  An interactive presentation by Zuken and Synopsys on a unique and innovative solution to characterize signal integrity analysis of ddr3 high-speed memory interface. As DDR is becoming more and more a hot topic (as seen at CES and with the recent Intel expected move to DDR4 memory), I am expecting this presentation to be appealing to a lot of signal integrity users.

I will be further describing this approach next week with the presenters.

  •   A unique PLL tutorial “Modeling PLLs for AMS Design and Verification” that would give you insights from both an “intra-PLL” modeling aspect (i.e. modeling interactions inside the PLL) and “inter-PLL” modeling one (modeling complete PLLs for interaction in the greater system). I worked on PLL modeling for several years and I think this tutorial will be really educational.


In addition to that, Synopsys will be hosting its annual HSPICE SIG event. This year, the SIG presentations will focus on signal and power integrity analysis of multi-gigabit serial links. HSPICE combines transistor-level accuracy with comprehensive signal integrity analysis, and is the golden reference for IBIS and IBIS-AMI modeling. In addition, HSPICE is integrated with major electromagnetic solvers and SI environments. So it complements extremely well DesignCon areas of interest and we hope to see you there.


So as you can clearly see, busy month for AMS 🙂

Hope to see you at some of those events. As usual, if you have any technical questions on any of those topics, feel free contact me.

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