Posted by Hélène Thibiéroz on January 9, 2014
Happy new year ! I chaired and organized a panel on Mixed Signal Verification at MTV 2013 conference last December and wanted to share some of my insights with you.
In just a decade, the landscape of mixed-signal design has drastically changed. While API simulations between a digital and analog solver have evolved into a more complex mixed-signal environment that includes multiple languages and technologies, those changes are still not enough to address today’s challenging design needs.
While the future of mixed-signal verification is unclear due to the diversity of use models and needs, you can still see some emerging trends, particularly for digitally-driven mixed-signal system-on-chip (SoC) design teams. I therefore wanted to explore and highlight in a panel those emerging trends and asked technical experts from various backgrounds to join me in this discussion at MTV 2013 conference:
Several topics were discussed, from new behavioral modeling standards to Digital verification techniques applied to mixed-signal and Debugging/regression mixed-signal environment.
The panel included both professionals from several major design houses (Intel, Freescale) as well as EDA vendors. I have asked one of our speakers, Ron Shebel, to present his views and insights.
Ron received his BSEE from Purdue University in 1989. He joined Motorola/FreeScale Semiconductors from 1989 to 2004 as a Memory Designer specializing in Memory Compiler design and custom SRAM design. He then joined Synopsys Inc in 2004 and is currently a Senior Staff Application Engineer focusing on Spice-Fastspice and Mixed-Signal Verification.
Question 1 : Hi Ron, you were one of the panel attendees, What was your overall impression and takeaways for this event?
Ron- The event was well received and attended. As for the panel discussion itself, I think there was a lot of interaction between the panel and the audience. The main points that came across were that Mixed-Signal Verification is key in the design of SOCs but there are many challenges in regards to debug of these simulations as well as shear thru put of the simulation engines. This is why higher level modeling is also needed.
Question 2- New Behavioral Modeling Standards: Various modeling methods (SystemVerilog-AMS, SystemC-AMS) are emerging today to resolve some existing limitations when passing information between analog and digital blocks within a mixed-signal SoC. What were the original motivation and goals behind these language enhancements? What are their current status?
Ron- The basic reason for these new behavioral standards is to allow more modeling options outside of the traditional Spice –Verilog. There are also some known limitation with some of the existing languages today, creating bottlenecks and need for workarounds while working at the top-level. The validation of complex systems which includes the verification of IP spice blocks is becoming more of the norm than in the past. Synopsys is actively working with leading edge customers to implement new standards. One emerging standard is SystemVerilog-AMS, where AMS constructs are being added to SystemVerilog to allow users to alleviate the bottlenecks that exists with traditional spice simulations. Another standard that we at Synopsys are embracing is SV-nettype which make system Verilog much more power in terms of real number modeling. Synopsys is actively working with main SoC customers on this implementation.
Question 3- Digital Verification techniques applied to Mixed Signal: There is a crucial need to port proven digital verification methodologies into mixed-signal SoC design. Industry standard verification methodologies have been enhanced with new analog-focused capabilities to extend for mixed-signal verification. What are the features and advantages offered by such flows?
Ron- The biggest advantage that I see is the direct re-use of digital testbenches within a Mixed-Signal environment. Digital concepts such as coverage, assertions, checkers are enhanced to work in a Mixed-Signal environment. Because we have seen our main SoC customers evolving from a Digital only to a mixed signal domain, Synopsys has implemented for a few years a methodology allowing to extend your Digital methodology to Mixed-Signal. Synopsys AMS testbench (previously called UVM-AMS) offers assertions, checkers, testbench generators that can be applied to analog entities. We have now several large customers using and looking at this technology.
Question 4 -Debugging/Regression environment: A mixed-signal environment has multiple facets, depending on a design team’s use model. Which features should such a debugging and regression management tool include to meet tomorrow verification needs?
Ron- Debug is key to Mixed-Signal Verification. A mixed-signal GUI that allows not only invoking simulations but also debugging is critical. Being able to transverse both rtl code and spice netlist as well as point and click features to see the exact states and voltages is what is needed. Moving forward, there would also be a need to coordinate digital and analog methodologies to ensure maximum coverage and bug detection. Synopsys by leveraging different tools (Verdi from the digital side and SAE for the analog one) is actively working on implementing specific features to debug specifically for mixed signal designs.
Thanks Ron and thanks to all for reading. If you have any questions regarding this event or any of Synopsys offerings, feel free to contact me anytime.