DVCON Europe: Extending Proven Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS
Greetings !
Posted in Uncategorized
VCS AMS joint webinar with Synopsys, ST and ARM : latest insights on advanced mixed-signal verification
Happy Tuesday,
Posted in AMS Assertions, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification
DAC 2014 AMS panel videolog now available
We hosted a few weeks ago at DAC Synopsys AMS luncheon with speakers from Micronas, Infineon, AMD and ST. The theme of this year’s event was “Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier”.
Posted in AMS Circuits, AMS EDA tools, analog, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification
DAC Synopsys AMS Technical Luncheon Panel – Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier
DAC is here and we are ready!
Posted in AMS Circuits, AMS EDA tools, Mixed Signal/Cosimulation, Uncategorized, verification
VCS AMS – Synopsys advanced mixed-signal verification solution to accelerate regression testing of mixed-signal SoCs
You may have seen Synopsys recent announcement during SNUG:
Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification
DVCON 2014 – Panel on Mixed Signal Verification: what’s next ?
For Mixed-Signal afficionados or wannabes attending DVCON, I will be moderating next Monday a panel session on Mixed-signal verification (not on French wine making yet, sorry 🙂 ) . This event is sponsored by Accellera and more information can be found at:
Posted in AMS EDA tools, Mixed Signal/Cosimulation, verification
Synopsys/Zuken at DesignCon- Unique DDR capabilities using WaveView and HSPICE
You may be tired of hearing only about Mixed-signal verification, so why don’t we switch to signal Integrity? :). Looking at the recent announcements at CES and Intel’s expected release of server solutions using DDR4 memory later this year, I wanted to further explore this topic. We had a little time ago a very successful webinar that showed in more details DDR capabilities that SI users have and are currently adopting using a combined Synopsys- Zuken flow. Because of our customer testimonies and their enthusiasm on those capabilities, I therefore asked the owners (Griff, Hany) to demo this flow at DesignCon at the ChipHead theatre (see link below) and to talk to us a little more. Our Synopsys WaveView expert Manu V. Pillai is joining the discussion as well to provide more insights on WaveView, which is used by this flow.
Posted in AMS Circuits, analog, analog design, Signal Integrity, SPICE, Uncategorized
HSPICE SIG, DesignCon, Busy month for Synopsys AMS
As DesignCon conference approaches and as the chairman of the AMS track, I would like to inform you on a few technical events happening there. In addition to our AMS track, we have added several events:
Posted in AMS EDA tools, analog design, Device Modeling, Mixed Signal/Cosimulation, Signal Integrity
MTV 2013 AMS Panel – The Future of Mixed-Signal Verification: from Simple Simulation to Full Regression?
Happy new year ! I chaired and organized a panel on Mixed Signal Verification at MTV 2013 conference last December and wanted to share some of my insights with you.
Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification
