Analog Simulation Insights


Optimizing your Mixed Signal Verification Environment using CustomExplorer Ultra – Part 2

Blog on Wednesday, Happy hour on Friday 🙂

I recently got several opportunities to discuss with many verification-driven companies on their needs for a powerful regression testing and verification environment. As such, in this post, I decided to show some features of Synopsys CustomExplorer Ultra (also labeled as CXU) that directly address your verification needs.

Synopsys CustomExplorer™ Ultra (CXU), is a GUI- and netlist-based verification platform that helps automate Verification regression tests without manually creating different configuration files or scripts.

CXU being a very versatile platform, you may have seen already several success stories on its use model:

That time, we will be focusing on regression testing. I have asked Paul Chapman to show us a demo and comment on his user experience.

Paul Chapman is currently working in Synopsys as a senior application consultant. After 10 years of mixed signal design at board level and full custom chips, he joined Analogy, an EDA company, in 1996 as an application engineer, worked for Avant! (hspice ), Neolinear ( Neocircuit Circuit sizing / optimization ), Cadence ( Virtuoso ), CSR (analog CAD), Magma ( Finesim), and finally Synopsys.

Glad to have you on board Paul 🙂


Q- Bonjour Paul ! Regression – it’s a word that brings few happy thoughts, especially for AMS Designers. As an EDA user that has been exposed to multiple environments, can you share some insights with us ?

Bien sur Helene :). We think of ourselves as a creative bunch; a fascinating blend of inspiration and the technical ability to take our ideas beyond dreams into everyday practical reality. However the true value of our designs is not when everything is good, but how they cope when temperature, chemistry and old age are against them.

With modern concurrent design methods and processes far more ECO’s happen late in the design cycle. Regression testing is what tells you if your design has unexpectedly degenerated, and so is very much needed to reduce the risk of a re-spin, or low production yield. Testing (boring) then documenting (more boring) is not why we chose to be engineers. Even a simple analog block needs dozens of tests to verify it across corners. All the AMS blocks of an SOC can easily reach many thousands of tests – too many for existing design environments. With reuse of IP and layout dependent effects we should verify the golden data – the netlists – that drive both simulators and physical implementation, but then cross-probe to schematics when available.

Q- Being an expert user of verification environments in general and Synopsys CustomerExplorer Ultra (CXU) more specifically, can you further comment on its capabilities as a regression environment?

Two of the objectives of Custom Explorer Ultra (CXU) are to make running tests relatively painless, and if a failure is found to help quickly find the cause. The demo shows setup and testing of a simple block. Results of the tests are collated and exported to standard office tools for reporting.



Make a habit of adding each block to your tests, and you don’t need to fear that changes of design or PDK have regressed your creation back to a knuckle dragging Neanderthal. An overnight run will easily confirm all is well, or point the way to where you need to make an adjustment. Although we have limited this example to pure analog block, CXU supports mixed signal simulations and Circuit Check analysis to provide comprehensive verification.

CXU also includes multiple features and flows that help keep the tedious bits to a minimum, and giving you more time to dream and create, or just get home before my dog gets my dinner !


Thanks Paul !

You can find more information on CustomExplorer Ultra at:

More info and videos to come on CXU soon. Meanwhile, feel free to contact me anytime or append your well appreciated feedback 🙂

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