Posted by Hélène Thibiéroz on March 7, 2013
Yes it is Thursday again 🙂
We had another successful event on Mixed Signal Verification at DVCON 2013. Because DVCON is a conference focusing on Digital Verification, Martin Barnasconi and I were able to showcase Mixed Signal Verification from a traditional/Analog Standpoint to a more Digital/Systemlevel approach. I posted a few weeks ago a description of our tutorial (see below), I therefore wanted to give you a summary as multiple topics and opinions were shared.
With that in mind, I have asked several of our speakers (see names and affiliations below) to give us their insights and impressions on this event:
Christophe Curis – STMicroelectronics
Ozan Erdogan – Maxim Integrated Products, Inc.
Martin Barnasconi – NXP Semiconductors
Thilo Voertler – Fraunhofer IIS
Thang Nguyen – Infineon Technologies AG
Q- can you summarize in a few lines (less than 4 sorry:)) your presentation on Mixed Signal Verification and the challenges you are trying to address?
Christophe (ST):The complexity of the IPs we are developing for modern SoC is increasing, growing from analog design to analog and digital interwoven. My presentation tried to present one of those small systems, which has a strong focus on analog, thus requiring more complex mixed-signal environment for its validation, with the performance versus accuracy challenge to address for designer’s reactivity needs.
Ozan (Maxim): The biggest challenge in mixed-signal SoC verification is the time it takes to run full chip simulations. I presented a methodology for speeding up functional verification of mixed-signal chips by modeling analog sections in SystemVerilog.
Martin (NXP): For automotive products, it is essential to guarantee a fail-safe IC implementation, compliant with the system specification. Therefore verification both at the system- and IC-level becomes very important, which should also include the interaction between the analog, digital and software functions.
Thilo (Fraunhofer IIS): At Fraunhofer and together with our “Verdi EU project” partners, we are working on a new verification methodology, especially targeted at the verification of system models using SystemC/AMS. In addition this new methodology will bridge the gap between simulation based verification and measurement oriented lab validation.
Thang (Infineon): The tutorial presents a hardware assisted verification approach using FPGA and AMS test chip. The approach proves to overcome those mixed-signal verification scenarios which simulation is not suitable, e.g.: long-term test (up to 5 hours of system operational time) with millions of sensor frames (analogue format) transmission. The approach is also used to accelerate the verification and lab validation.
Q- Looking at this tutorial, it is clear that Mixed Signal Verification landscape is fairly vast and may require different flows depending of your design and industry needs. In your industry, how do you see the future of Mixed Signal Verification evolving?
Christophe (ST): In the domain of mixed-signal IP development, the AMS extensions to the languages is already providing a number of solutions to today challenges, yet its usage will have to expend more amongst designers. There will be a need to ease the use of these technologies to help conceiving future IPs, which will integrate more and more complex analog and digital interacting together and better flow support.
Ozan (Maxim): As the chips we are building gets more complex, we will use a mix of tools to achieve first silicon success. At top level high level languages, such as Matlab, can be used for quickly exploring the design space, in the next level implementation assumptions can be checked with analog behavioral languages, such as Verilog-AMS, and for full chip verification we will see more and more behavioral modeling for pure digital simulators for speed.
Martin (NXP): Mixed signal verification approaches will more and more use techniques inherited from the digital verification domain, like functional verification approaches based on UVM. However, we still need to extend and customize these digital-centric methods, as we deal with analog, continuous-time functions. Besides some language challenges, we also have to learn how coverage-based and assertion- based techniques can be applied in the mixed-signal domain.
Thilo (Fraunhofer IIS): To understand and verify AMS designs at the system level, we see that simulation speed and model complexity are the key challenges to scale verification to larger designs. Therefore easily understandable and fast behavioral models are needed e.g. written in SystemC/AMS. On the verification methodology side support for digital techniques like UVM should be integrated to allow the reuse of existing VIP.
Thang (Infineon): Complex mixed-signal SoC products with high number of functionalities integration has also recently become a trend for automotive electronics industry in the future. The verification in such automotive SoC product is even more challenging as there are still a high number of analogue interfaces to the physical world and a number of the application has to deal with the new safety standard ISO 26262, e.g.: braking, airbag, electronic power steering system, and etc. Verification of such product in the context of ISO 26262 does not only to comply the specification but also to functionally verify the product in its application circuit with sensors and actuators. As well as, time-to-market and first time right design are key requirements in project to win customer and market share. For the future of Mixed-Signal Verification, a right verification strategy and a comprehensive combination between different tools and methodologies – e.g.: from classical approach of mixed-signal simulation with directed test, to using advance methodologies UVM/UVM-AMS or FPGA and emulation platform – will become crucial skills. The acceleration of verification and validation will become also an important topic in the future as the product complexity is increased while the cost per silicon area is decreased.
Q- Besides the fact that your track organizers are plain awesome :), do you have any takeaway from this tutorial you would like to share?
Christophe (ST): It has highlighted that there are two trends in AMS modeling, the big system world (SoCs) which can tradeoff the accuracy of analog modeling in AMS (through real numbers) for performance due to the size of their systems, and the mixed-signal IPs which can benefit from lower-level, more accurate modeling to better validate the interactions between analog and digital blocks in small systems.
Ozan (Maxim): We received some great questions from the attendees, it was clear that the tutorial was very relevant to today’s mixed-signal SoC verification challenges. It was great to see such a variety of verification approaches in one tutorial.
Martin (NXP): I noticed that the leaders in mixed-signal verification start using object-oriented languages like SystemC and SystemVerilog to get the job done. There is clearly a need to have more expressive languages to create advanced mixed-signal testbenches and also offer features to further abstract the analog signals. It becomes clear that only real-value-modeling is not good enough.
Thilo (Fraunhofer IIS): Coming from Fraunhofer, a research organization with the mission to bring newest scientific results into industrial practice, it has been a great experience being to DVCon and getting lots of feedback from industrial users but also having the chance to talk to EDA vendors
Thang (Infineon): The tutorial session was very information and successful. It did cover a wide range of challenges related to mixed-signal verification within different industrial applications. Even though digital verification becomes more and more dominant, I would stress out that mixed-signal verification will still be a challenge in the coming years, especially for automotive electronics industry. This tutorial session should be kept running so that authors with different application back-ground could share their end-user experience in the field of mixed-signal verification.
Thanks to our speakers for their valuable insights. If you have any comments/questions or are interested in this tutorial, please let us know.
Hope to see you next year !