Analog Simulation Insights


DesignCon Panel on Behavioral modeling summary report- you have all been waiting for it :)

Blog post on Thursday, Happy hour on Friday… so I had to release it today:)

We had a few weeks ago a very interesting and interactive panel on AMS Behavioral modeling at DesignCon. I therefore wanted to share this discussion with some of you that may have not been able to attend. Behavioral modeling for AMS being a very wide topic, I wanted to ask questions pertinent to Analog, Mixed-Signal and RF to see if we could draw correlations or some high level common themes between domains. With that in mind, I asked to our panel attendees a series of questions aiming to generate some reaction in our panel as well as in the audience. It looks like it worked 🙂

The panel description can be accessed at:

I have asked two of our panelists,  Shayan Farahvash and Richard Shi, to share with us their answers to some of the topics discussed. I am always interested to hear your comments and thoughts so feel free to add anything to this post.

Shayan Farahvash is a senior principal engineer with Maxim integrated, where he is in charge of architecture selection, product definition and algorithm development for cellular transceivers and radio tuners. Prior to Maxim, Shayan was with Hughes and RFMD, where he led transceiver and synthesizer development from sub 1-GHz to millimeterwaves. Shayan also established mixed signal verification flows in RFMD using behavioral modeling in Simulink, ADS and System Verilog. He holds a PhD from Penn State University and he has been granted two US patents with several more pending.

Richard Shi is a founder and CTO of Orora Design Technologies, Inc, where he leads a team pioneering automated analog abstraction for mixed-signal design and verification.  He is also on leave from the University of Washington where he is a professor in Electrical Engineering. He is elevated to a Fellow of IEEE for his contribution to computer-aided design of mixed-signal integrated circuits, and has worked on SPICE and behavioral modeling since 1983.

What was your main motivation for using behavioral modeling? Top down design approach for first path verification? Performance?

Shayan: Performance verification is rarely a reason to perform behavioral modeling, specially in  wireless applications. Behavioral models, very appropriately,  only capture some operational aspects of a high performance analog/RF circuit, so they are a poor substitute in brute-force circuit simulation with all the layout parasitics included. On the other hand, verifying the functionality of a high-performance circuit, specially as a part of a larger system, is unnecessarily complicated without using behavioral models.

Richard: Behavioral models were firstly used for top-down analog design, and recently we have seen from our customers the increased use of behavioral models for first path verification, both functionality and performance. Automated behavioral modeling is emerging to bridge the gap between top-down design and bottom–up verification. This is especially true for 28nm/20nm mixed-signal system-on-chip design.

How long is too long for a verification/top level simulation run? At what point do you decide to look for behavioral modeling to speed up your simulation and gain performance versus accuracy?

Shayan: If objective is performance verification, then simulation time is irrelevant: you simulate as long as it takes. This rule is generally applicable except for PLL’s, where circuit simulation has scale of weeks instead of days. For PLL’s, some sort of combined behavioral and circuit models is the optimal choice. To say the obvious, this has to be done carefully. For instance, if you model frequency dividers don’t forget to about their additive jitter.

Richard: We have seen that our customers run a verification/top level simulation for one month at 20nm/28nm nodes! The wish is 1 day for verification. The key issue is to increase the simulation coverage of various configurations, where at this moment, designers typically run simulation for 1 case. Behavioral modeling is essential to speed up the simulation. Behavioral modeling can be very accurate but with less unwanted details.

Who should write behavioral models?  Designers? Verification engineers? Modeling experts?

Shayan: Designers for sure. No one else has the intimate knowledge of a circuit to write a behavioral model for it.  Delegating this responsibility  to verification engineers is highly inefficient because they must first understand the subject circuit and then work with a designer to ensure that the behavioral model captures the essence of that circuit. This is a long and error-prone process. Instead, verification engineers must focus on functional verification at top level and report any non-compliance to designers to see if it was a symptom of a real circuit defect or a mere modeling error.

Richard: For verification, behavioral models shall be generated from schematics or post-layout netlist by designers using automated tools, and shall be qualified by verification engineers. Modeling experts will be responsible for setting up the methodology together with designers and verification engineers. For top-down design, designers shall write models as specification incorporating verification requirements from verification engineers, with the assistance from modeling experts.

How do you deal with true mixed signal blocks and circuits: model it in the analog domain, in the digital domain, or really in both domains? Which factors do you use to determine architecture and flow to use?

Shayan: The best approach is a mixed one: combine digital and analog models. RTL languages are a poor vehicle to write a behavioral model for an analog circuit since they don’t have the primitive constructs for a mathematical model of an analog/RF circuit. Similarly, VeilogA  has a very limited capability to model binary, event-driven, discrete time systems.

Richard: We predict that the future of mixed-signal modeling will be at the two extremes: (1) digital on top, then analog blocks will be modeled using Verilog-D/REAL, simulated and verified by digital simulators, and (2) analog on top, both analog blocks and digital blocks will be modeled in Verilog-A, and simulated by high-performance analog simulators. Purely digital simulators and purely analog simulators will dominate mixed-signal verification, as enabled by automated bottom-up behavioral model generation from SPICE netlist. We continue to believe that the future of mixed-signal simulation and co-simulation will be limited.

How do you see behavioral modeling evolve in the next five years for Analog, RF and Mixed-Signal?

Shayan: We will see that behavioral modeling becomes an integral part of the design flow. Today, such models are generated and used in system-level verifications on a “need” basis. Every increasing complexity of the coming analog/RF chips combined with ever increasing development cost and low tolerance for failure because of “silly” mistakes will foster an environment that makes the behavioral modeling and system-verifications compulsory.

Richard: In five years, behavioral modeling will be used by every analog, RF and mixed-signal designer, and automated behavioral modeling will be ubiquitously embedded in every step of mixed-signal design flow. All the leading simulators (analog, digital and mixed-signal) will have the robust support of behavioral modeling languages.

Thanks again to our panel attendees for giving us such a great session.

DVCON tutorial summary report will be next 🙂

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