Posted by Hélène Thibiéroz on February 21, 2013
Happy Thursday !
I have been asked to be co-chair at DVCON for a tutorial on Mixed Signal verification (yes, what a surprise :)) in collaboration with Martin Barnasconi, from NXP. We therefore use the best of our brain cells to put together a tutorial that highlights the latest innovations in Mixed-signal design and verification. I have listed the link below to this event:
Because DVCON is a conference focusing on functional design and verification, we recruited experts to talk about the latest advancements in mixed-signal design and verification as well as current and future challenges they foresee. Topics in this tutorial cover the application of the Universal Verification Methodology (UVM) in the mixed-signal domain, usage of VHDL-AMS or Verilog-AMS for AMS verification, and the introduction of mixed-signal features in SystemVerilog or SystemC to enable verification at the system-level. Whether you are working on extending your digital verification methodology to AMS or looking for ways to improve performance of your analog flow by leveraging digital verification techniques, this tutorial is a must see.
Our speakers are (in chronological order):
Henry Chang – Designer’s Guide Consulting, Inc.- Common Mistakes Made in Analog Verification
Jonathan David- Qualcomm – The Mixed Signal Verification Challenge
Christophe Curis – STMicroelectronics – Mixed-Signal Validations for a BIST on ADC
Ozan Erdogan – Maxim Integrated Products, Inc.- SystemVerilog Modeling for
Mixed-Signal SoC Verification
Martin Barnasconi – NXP Semiconductors – AMS system-level design and verification for automotive applications
Thilo Voertler – Fraunhofer IIS- Mixed Signal Verification and Validation for SystemC/AMS
Thang Nguyen – Infineon Technologies AG – FPGA and AMS Test chip Approach for complex SoC product design and verification
The order is fairly logical: we start with analog verification challenges (Henry) , continue with mixed signal verification using a traditional behavioral modeling approach (verilogams- Jonathan/vhdl ams- Christophe) and SystemVerilog/ real number modeling (Ozan). We would conclude this user experiences tutorial by looking into more advanced topics (systemC –AMS, Martin and Thilo) and finishing with a more hardware centric approach (Thang).
Each user would present his methodology for 20 minutes, followed by a Q&A. We will then wrap up the session with a general Q&A where pro and cons those approaches would be discussed and compared.
By offering a depth and breadth of understanding of a full spectrum of current and developing technologies, I believe this tutorial would be extremely valuable to anyone involved with Mixed signal verification. We had a very animated panel at DesignCon on behavioral modeling, so I am hoping to reproduce the same dynamics for this Mixed signal Verification tutorial 🙂
Hope to see you there !