Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, semiconductor design is no longer confined to “semiconductor” companies. In the past few years, many electronics, communication, and computer equipment companies have brought ASIC and SoC design activities back in-house. They now consider these designs to be competitive differentiators and crucial intellectual property rather than commodities that should be outsourced. This is – in significant part – driven by an increase in mathematical algorithmic content being engineered into signal, image and video processing, and mixed-signal designs
I know, it’s been a while… )
Posted in Uncategorized | Comments Off on DVCON Videolog on “User Experiences at the Forefront of Mixed-Signal Verification” now available
Happy Thursday ! I can’t believe it is already end of July…
Well after a couple of busy weeks traveling (and I am sure you really care about knowing this :)), I finally found some time to blog about our DAC AMS event held in Austin early June. We had a very successful event with some great technical presentations (hey that’s the feedback I received from the crowd..) from Micron, Broadcom, ST-Ericsson E, ARM and ST-Microelectronics. The topics ranged from low power and reliability and mixed signal verification and advanced memory characterization.
DAC 2013 AMS Verification Luncheon: Advance Your Mixed-signal Verification Techniques to the Next Level
Posted in AMS Assertions, AMS EDA tools, Mixed Signal/Cosimulation, Reliability, verification | Comments Off on DAC 2013 AMS Verification Luncheon: Advance Your Mixed-signal Verification Techniques to the Next Level
Blog on Wednesday, Happy hour on Friday 🙂
Synopsys Invited FinFET talk at WMED: Q&A on FinFET variability and its impact on digital and analog circuits
If you have been following my blog, you may have noticed a couple of posts on FinFET technology, mostly on the modeling side. I recently worked with the WMED committee to look at innovative subjects (especially for those spots after lunch time :)). One topic we selected was the challenges faced by analog and digital designers when using a FinFET based process.
Attractive title, isn’t it? 🙂 I wanted to share with you some benchmarks we conducted with key partners using Discovery-AMS multi-core technology. This feature is available in 2013.3 release for Mixed Signal Verification and allows you to considerably speed up your simulation. Two key advantages of Discovery-AMS are performance and versatility. By combining the efficiency of a Fast-Spice solver with multithreading, we were able to boost performance up to 10X.
Posted in AMS Circuits, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | Comments Off on Q&A with STE: How to speed up your Mixed Signal Verification with no accuracy loss??
Yes it is Thursday again 🙂
Posted in AMS Circuits, AMS EDA tools, Behavioral Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, verification | Comments Off on DVCON 2013 Mixed Signal Verification tutorial: Insights from our Speakers
Blog post on Thursday, Happy hour on Friday… so I had to release it today:)
Posted in AMS EDA tools, analog, analog design, Behavioral Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, RF, SPICE, Uncategorized | Comments Off on DesignCon Panel on Behavioral modeling summary report- you have all been waiting for it :)