Analog Simulation Insights


Optimizing your Mixed Signal Verification Environment using CustomExplorer Ultra – Part 1

With increasing complexity of mixed-signal designs comes a more and more expensive coverage scheme for verification, from the analog as well as the digital side. Finding a verification cockpit combining ease-of-use, performance and required features for both Analog and Digital is therefore not a trivial task.

If you think about it, you need an environment able to support both Analog and Digital domains, all potential configurations as well as various language extensions (SPICE, Verilog, VHDL, VerilogA, VerilogAMS,….). You also need to cover a large design space, requiring an efficient way to run multi tests in parallel, to display both analog and digital results simultaneously and troubleshoot any accuracy/convergence issues.

With that in mind, I wanted to further develop on Synopsys CustomerExplorer Ultra and how this platform fits today verification needs. But rather than just giving you a list of features or a datasheet, I wanted to focus on key points of CXU using small videos. I know, I am a nice person 🙂

I have therefore asked several CXU experts to demo some of those features. In this 4 minute video, Manu Pillai is showing us the spice debugging features of CustomExplorer Ultra’ s Connection View:

Multi-net connectivity/Full schematic display: CXU’s Connection View is highly interactive. It accepts the designs in the netlist format and allows the user to display the signal path relevant for the debugging. It is capable of showing the connectivity of multiple nets and complete schematic, so that user can visualize their netlist .

Waveform Cross Probing: User can link the existing or newly created waveform file with the Connection View and cross probe the signals. This is very useful for the debugging purpose.

Parameter report and W/L report: Netlists may have lot of parameters with expressions and CXU will evaluate these expressions and gives the parameter report. The W/L report gives the width & length information of all the MOS devices in the design. These reports will be useful to identify unreasonable parameter definitions or width and length values.

Enjoy the movie 🙂

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