Analog Simulation Insights


Rambus significantly speed up their DFT Logic and Timing Verification in Mixed-Signal Designs using CustomSim-VCS

In our latest blog entries, Synopsys mixed-signal customers talked about their verification flow. Those posts described known aspects of mixed-signal environment (such as for example behavioral modeling). I wanted to highlight today a slightly different usage of Synopsys mixed signal solution among some of our customers. Using performance and ease of use of CustomSim-VCS, DFT verification engineers are able to get a considerable speedup in their simulations.

Of course, when I am referring to DFT, I am not talking about Fourier Transform, but Design For Test 🙂

Rambus is one of those customers. Working closely with Synopsys, they presented a paper on this approach. The goal was to use CustomSim-VCS to drastically improve DFT  logic and timing verification cycle-time and coverage.

In this interview, Bing Chuang from Rambus and Sumit Vishwakarma  from Synopsys share their  insights about using CustomSim –VCS  for DFT Logic and Timing Verification, the flow they architected  and the improved coverage and performance they were able to get.

Bing Chuang  received the B.S. degree in Computer Engineering from the University of California, Santa Cruz in 2004, and the M.S. degree in Computer Science and Engineering from the Santa Clara University in 2006. In 2006, he joined the technical staff at Rambus, where he has engaged in design-for-test and verification of high-speed mixed-signal designs.

Sumit Vishwakarma graduated from Arizona State University where he worked on Intel research project on ultra wide band technology. On graduation he published IEEE paper on UWB front end design and joined Synopsys in 2004 as an application consultant for Synopsys RF tools. His role later got extended to support full Analog Mixed Signal products. He current has five SNUG publications in the field of AMS.

Q-  Could you please describe your job responsibilities? What kind of circuits do you typically design (Bing)?

Bing Chaung

My primary job responsibility is to ensure manufacturing success in all Rambus’ semiconductor designs through the architect, implementation and verification of DFT test structures. Examples of test structure I verify are traditional scan, boundary scan (including both DC and AC JTAG), memory built-in-self-test and at-speed scan logic. I also conduct coverage analysis for various designs to help improve test coverage and yield. My secondary responsibility is to enable quality first-time-right designs through CustomSim-VCS verification infrastructure support, mixed-signal design timing coverage analysis and analog behavioral model verification.

Q- Since AMS engineers do not deal with testability every day, can you briefly tell us about DFT and its benefits. (Bing)

Design for Test (DFT) is about testing if a chip is manufactured correctly (not to verify logic behavior). Manufacturing tests validate and ensure that the product hardware contains no defects that can cause the product to function incorrectly. In the manufacturing flow, tests are generally performed by Automatic Test Equipment (ATE) at various steps of the fabrication process. Test can be applied at the wafer level, but is usually limited by the number of pin contacts. Test can then be applied at the module level after packaging is completed.

There are two types of test generally used in manufacturing. The first is functional test which focuses on the functional specification of the circuit while structural focuses on screening the product for defects or faults. Fundamental testing principle is to make sure every node can flip between ground and supply. One common fault to test for example is called stuck-at fault where a node in the circuit is shorted to either ground or the power supply. The goal of structural test is to validate that all logic gates in the circuit are operating and connected correctly.

Q- Only a few designers use DFT flow for mixed-signal simulation. Why is this flow not widely adopted within Mixed-Signal community? (Bing)

There are three common reasons why DFT are not commonly designed into a custom logic circuit.

  • The coverage gain is typically not high due to the presence of analog blocks. It is not worth the effort if the custom logic portion is a very small proportion of the overall design and can be somewhat covered by functional testing.
  • ATPG tools can only read in designs in Verilog format, not in transistor formats. Some expertise is required to put together a gate level model for running ATPG.
  • The lack of a known DFT flow is a major factor in deciding against including DFT test structures in the custom logic circuits.

Q- How is Rambus using Synopsys Mixed Signal solution to make this successful? (Bing, Sumit)

Bing: The design team implements the test structure through two ways:  digital place-and-route (P&R) and custom logic. For the P&R method we use scan insertion tool(s), while the custom logic portion is done by hand stitching the scan chains.

Since there are no commercial ATPG tools for transistor-level design, we create a gate-level design, with functionality equivalent to the transistor-level design. The gate-level design works as a model for the transistor-level design and can be used by the ATPG tool to create vectors that can then be applied to the transistor-level design (refer top part of figure). For simulation we use CustomSim-VCS cosimulation since the testbench/vector output from the ATPG tool is in Verilog format. Rambus DFT flow is ATPG tool neutral but we used TetraMax to generate the APTG vectors.

Sumit: To achieve orders of magnitude of performance Rambus uses some smart techniques available in CustomSim-VCS Co-simulation. In real world, when the ATE tests the chip, it loads the vector onto the chip, from a primary input pin by serially shift in the Vectors into the scan chain. It takes 1,000 clock cycles to shift in a 1000 bit vector onto a 1,000 bit long scan chain. This operation is done over and over again until the testing is complete.

A simulator can simulate the same but this can be terribly lengthy simulation and really not needed to convince that the scan chain does function correctly. A simulator have the luxury of bypassing physical limitation (of loading an external vector onto a shift register via lots of shifts), it can simply force a vector bit onto a scan register or force the whole vector onto the whole scan chain. This parallel loading can save lot of simulation cycles, however to in order to simulate a parallel testbench, the simulator must be able to handle cross module references (or XMRs) between the boundaries of Verilog block and transistor level blocks. CustomSim-VCS co-simulation offered this functionality which resulted in orders of magnitude speedup.

Q- Rambus adopted this flow in production. What motivated this decision ? (Bing, Sumit)

Bing:  This flow arms us with a sign-off methodology to do DFT for transistor-level design which is conventionally not done. By inserting test structures in custom digital logic, we have provided the ability to test the designs using industry standard ATPG tools. Secondly, parallel testbench DFT methodology is a reality with CustomSim-VCS Cross Module reference capability. This provides significant speed up as compared to serial pattern DFT. The flow enables both functional and timing verification of test structure (scan chains) in a matter of hours, not weeks of simulation.

Sumit Vishwakarma

Sumit:  Supporting and maintaining a complex flow which involves multiples tools and languages is not easy. However CustomSim-VCS co-simulation provides some pretty handy debugging features that makes a designers life easier. For example, it creates a separate directory which keeps all the relevant files at one place and avoids the clutter. These files can provide all the information at the A/D interface, A/D hierarchy, names mapping etc.  The flow we setup at Rambus has been a sign-off flow for few years now. Synopsys is also enhancing the flow by adding ‘save n restore’ capability in co-simulation which can further cut the simulation cycles for function/timing verification.

Thanks to Bing and Sumit for sharing their insights on this innovative flow.

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