Posted by Hélène Thibiéroz on July 31, 2012
Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.
In our previous post, we talked about VerilogAMS, which is one approach. In this post, I wanted to talk about an other approach, Real Number Modeling, and highlight the efficient solution developed co-jointly by ST Ericsson and Synopsys, which is based on Synopsys CustomSim-VCS VHDL- Real Number flow. Using this flow, ST-E was able to boost simulation performance and increase verification coverage of their most complex AMS chips.
Both flows (VerilogAMS and Real Number Modeling) are fully supported by Synopsys.
In this interview, Francois Ravatin from ST Ericsson and Philippe Brahic from Synopsys share their insights about using CustomSim –VCS VHDL real number flow and the drastic improvement they were able to get.
Francois Ravatin has joined in 1994 Thomson Consumer Electronic Components (ST Microelectronic – Thomson Multimedia joint venture) in digital libraries and tools support team. In 1998 he joined ST Microelectronics as analog mixed-signal designer in Wireless division and then Display division. He moved in 2007 as AMS verification engineer in analog & RF design flow group at ST Ericsson.
Philippe Brahic started in CSI laboratory (INPG Grenoble) as a research engineer, moved in 1996 to an EDA vendor working on spice simulator to finally joined Synopsys in 1999 as an application consultant. He is now focusing on Synopsys AMS products and has worked closely with ST and STE on numerous flows and applications.
Q- [Francois] Could you please describe your job responsibilities? What is your role within ST-E?
My job, as part of a project team, is to participate to ICs AMS verifications. I have also the responsibility, as transistor level verification expert, to define, put in place and deploy methodologies to achieve design-independent errors detection with transistor level IC description. Most usual errors detected are:
– Failure to reach power-on state (gets stuck in boot)
– Destructive currents and voltages
– Leakages in diodes (parasitic or not)
– Floating gates
These verifications are key verifications to achieve first time silicon success and reduce time to market which is mandatory with mobile phone market.
Q- [Francois and Philippe] ST-E worked closely with Synopsys on an extensive verification flow using CustomSim-VCS VHDL real number approach. Could you please describe this flow for our readers?
Top level verifications are a tradeoff between accuracy and simulation performances. In our flow we have chosen to use VHDL real number (VHDL-RN) to optimize run time for startup type of test case (from battery plug to power-on state) because this test case is the base for all others verifications. Obviously, to maximize coverage, each block used in VHDL-RN is also simulated at top level using a spice description.
We use VHDL-RN descriptions only for few blocks. Cells used with VHDL-RN models are classified in two categories:
– analog switched blocks (like bucks or boosts)
– clock generators (like oscillators or PLLs).
VHDL-RN is also used at the test-bench level for stimulus.
To give a more detailed description, VHDL-RN models for analog IPs are describing the functionality of the cell. These models also include checkers on some relevant signals in order to guaranty that the cell is in a typical functional environment. For example, checks are done on input voltage or current references, and also on input clock (frequency and duty cycle checks).
About the stimulus, our goal is to have only one stimulus to drive the design under test. This stimulus should be usable with digital verifications and fast spice verifications. VHDL-RN approach gives the possibility to mix the drive of digital signals and electrical signals in a same stimulus. So test sequence is easier to put in place. We are working on this point with Synopsys to have a convergence between stimuli.
A key feature for our verifications, available in CustomSim-VCS real number, and needed either for analog IPs models or stimulus, is the possibility to convert a real Hi-z level to an electrical Hi-z level. This feature is necessary when, for example, test case wants to reproduce a battery unplug after a battery plug. In this case battery node is first forced and then released. There, electrical high impedance is needed and CustomSim-VCS real number allows that.
This flow approach is enough to achieve power-on state of circuits with low run-time (between 1 and 2 hours) and this with around 300K to 400K transistors.
The strategy put in place was to work first on a design already verified by the “standard flow “ Csim-VCS VHDL and then to modify it to take in account all type of connections not present in the original test case. This approach has been the key point for this success. In a second phase we have enhanced our flow to be more users friendly.
Q- (Francois) Why did you select CustomSim-VCS VHDL Real Number modeling? What were the main compelling factors? How does this methodology compare with other behavioral modeling approaches?
We have chosen VHDL Real Number modeling methodology for several reasons.
The first reason, which was a great deal to do, was to have the possibility to create simulation setup easily.
Before using VHDL-RN methodology, we used to skip analog switched blocks and replace them by PWL sources, in the same way oscillators were replaced by PULSE sources. The goal with those skips was to optimize simulation time. But, as sources setup is test case dependent, this approach introduces difficulties to setup your test-bench.
Now, with VHDL-RN, we can get a better representation of the behavior by using RN models and the risk of errors is limited. This also means that the co-simulation configuration is easier to use from a test case to another one (no need to modify sources).
Second reason was that VHDL-RN models for analog IPs are already developed in STE for digital functional verifications, so we have the possibility to re-use verified and accurate models.
Finally, we wanted to improve simulation run time performances by using models for switched or clocked blocks and also using models for regulators used as internal supplies. We did see a drastic performance improvement by switching to VHDL-RN models.
Q- (Francois and Philippe) As you move with more advanced process nodes and more chip integration, which issues do you foresee/anticipate for mixed-signal verification?
Mixed- signal IC complexity is indeed growing more and more: complexity because of integration in a single chip of new functionalities with more complex architectures, complexity because of increase of number of devices,…. As such, the need for verifications arises accordingly.
Upcoming challenges will be on several points: capacity of EDA tools to accept larger design to verify; capacity to accept data with different formats (spice, VHDL, verilog, …) in order to have different levels of abstraction for verifications; providing more and more automation in the verification flow (like system verilog assertions for example) .
Cleary a UVM base flow would be a plus. Designers in charge of top verification cannot check manually hundreds of waveforms. Risk of errors is high and it requires deep knowledge of each Ip. The good news is that we have @Synopsys all these technologies available 🙂