Analog Simulation Insights


Q&A with ST-Ericsson: Latest ERC flow innovations using CustomSim CCK for optimal verification coverage

Circuit design implementation has become increasingly complex in deep submicron technologies. Multiple processor cores, I/Os peripherals, complex analog circuits, and logic are now being implemented onto the same chip. Ensuring product reliability to meet design goals and to achieve good yield has become a crucial step in today design cycle. With complex IP, system integration, and multiple power domains, you need an extremely flexible and powerful EDA solution to tackle those circuit verification demands.

Synopsys CustomSim Circuit Check (CCK) provides this solution:  it helps users to avoid wasted simulation time by finding design and performance problems automatically, reporting potential problems in a circuit before running simulation. You can find more information at

I therefore wanted to give you more insights on Synopsys CCK and how our customers are addressing those challenges.  ST-Ericsson presented at our European SNUG event a very innovative flow they developed in tight collaboration with Synopsys using CCK Dynamic ERC (Electrical Rule Checking) for an optimal verification coverage.

In this interview, Vincent Bligny from STE and Philippe Brahic from Synopsys share their  insights about using CustomSim CCK and the flow they developed at STE to detect dynamic HiZ, current leakage and overvoltage on thin oxides.

Vincent Bligny first joined STMicrolectronics PDK team in charge of device models integration and component libraries. He then joined the analog & RF design flows group in charge of power integrity and reliability analysis. He’s now in ST-Ericsson, responsible for transistor-level verification in ST-Ericsson for power-management, RF and SoC designs.

Philippe Brahic started in CSI laboratory (INPG Grenoble) as a research engineer,  moved in 1996 to an EDA vendor working on spice simulator to finally joined Synopsys in 1999 as an application consultant. He is now focusing on Synopsys AMS products and has worked closely with ST and STE on numerous flows and applications.

Q-  (Vincent) Could you please describe your job responsibilities? What kind of circuits did you simulate using CustomSim and which specific CCK features did you focus on?

Vincent– I’m responsible for IC verification at transistor-level, which implies the definition of methodologies and guidelines to detect all design-independent errors in time for PG. My commitment:  ensure that those errors happen only once in the company.

By design-independent error, we mean errors that occur on all type of designs such as:

–          Failure to reach power-on state – gets stuck in boot

–          Static and dynamic floating gate

–          Missing level-shifter or isolation

–          Any leakage in intentional or parasitic diodes, latch-up conditions

–          Electrical overstress and aging in standby modes

–          Oxide breakdown engineering: estimate product lifetime to release the voltage limits

–          Electrostatic discharge – human body and charge device models

The process of checking for those errors before PG is usually known as electrical closure (EC).

Q- [Vincent] can you describe this process in more details? Why is it so crucial for STE to include those verification checks in the design cycle?

Vincent Bligny

Vincent- All circuits in ST-Ericsson from 1M-transistor power management units to 1B-transistor SoC must be verified on a full transistor description before PG. Naturally, the types of verification applied vary to accommodate the needs and capacity of the tools. What shouldn’t change is the list of verification checks applied.

The transistor-level verifications can be split into 2 main categories: static [1][2] and dynamic [3].

Static checks are nothing more than a netlist exploration, “like a designer doing a schematic review” with the added information of voltage values that get propagated by CircuitCheck. The runtimes are stunning, from less than 1 min (on power-management designs) to no more than 5 hours (on a 700M devices SOC). In addition to its capacity, static checking is truly vectorless: all supply and signal values combinations are checked in one run.

All of the errors I mentioned earlier are now history in ST-Ericsson when they occur in digital topologies. That’s the main limitation of the static approach: when applied to analog structures (current mirrors, diff. amplifiers, etc.), it generates too many false positives. Those can easily be filtered to focus on real errors, but there exists a risk that an error in an analog topology is overlooked. A simple but effective way to identify such topologies is that they have quiescent current when operating.

There come the dynamic checks: the checks are applied on the voltages simulated by CustomSim. All false positives disappear in analog topologies. This check becomes vector-dependent, which greatly limits the coverage in digital parts. Our experience, however, is that going through the major operating modes of an IC is enough to cover most of the states of the analog circuitry: vectorless is mandatory for digital, but not for analog.

In short, the circuit is searched for errors described as “voltage condition on one or several devices”. For digital topologies, Synopsys CircuiCheck propagation is realistic and enables using a simple static checker. For analog structures, that have quiescent currents, the tool needs to go through an analog engine to determine the biasing state before applying the conditions.

One of the good surprises we had with rule-based checking is that the rules are very general:

–          A single rule: “channel leakage” usually covers many errors (missing levelshifter, isolation, improperly inserted levelshifter, etc.).

–          The rules are (with the exception of some numeric values) independent of the process (13µm to 28nm) and the foundry: the same set of rules has been used on all but one of the major fabs.

Transistor verification and error-based checks are a booming activity in ST-Ericsson, with two major development axis:

–          Inject more electrical awareness to static checks, more capacity to dynamic by considering both as just one tool

–          Extend the variety of checks and their understanding of the design (ex: use GDS2)

Q- (Vincent) Why did you select CustomSim CCK for ERC? What were the main compelling factors?

Vincent: Our choice of CustomSim was dictated by just one reason. We found CustomSim to be the only fast-spice engine that could simulate our mixed-signal designs without compromise on either coverage or accuracy:

–          No skipped blocs: all possible cause for errors included in the simulation

–          Simulation sequence is fully aligned on Silicon – all timings are actual

–          All currents 10% accurate vs. Silicon down to IP level – 1000s of measurement points

Before CustomSim, our circuits couldn’t be simulation with all analog IPs at transistor level: the average added-value of xa, on a large sample base, is that it saves one cut. Projects with lots of reuse now ramp-up on their first cuts; entirely new projects don’t need a 3rd cut.

The power of CustomSim analog engine is leveraged by more features that were gradually introduced by Synopsys:

–          A cosimulation flow for Spice+RTL mix or Spice + power-pins gate verilog mix

–          Dynamic ERC to find errors with no impact on functionality

–          Real-number in VHDL/Verilog for behavioral models of analog IPs (PLL, dc-dc)

We now envision a solution that covers 100% of our mixed signal verification needs from start-up on a transistor only DUT to complex functionality simulation with only few IPs in spice.

More than advanced features, we need Synopsys mixed-signal simulation to be reliable. Both coverage and verification schedule adherence must be 100% on all projects. We’re happy to report that this objective is met!

Dynamic ERC without a reliable simulation engine results in a flood of false errors: XA analog capacity and accuracy enables CustomSim CCK errors coverage boost.

Q- (Vincent and Philippe) Could you please describe at a high-level the paper you presented at SNUG?

Philippe Brahic

Vincent: A paper [3] has been presented at SNUG to describe some elements of the electrical closure process.

The paper gives more technical information on the building blocks of the closure process. The solution from Synopsys is presented in the context of a flow adapted for timely verification of ICs. The experience built after four years of practice is summarized as errors statistics, which is our motive for all developments in the electrical closure flow.

Philippe: The challenge on Synopsys side was not only to optimize the flow to reduce memory consumption but also to limit the number of redundant errors in the output file for an easy debug phase.

Last area of investigation was to add new capabilities specifically for STE: we worked closely with STE to implement dedicated interactive commands to extract on demand excessive current and Hz nodes detection.

Q- (Vincent and Philippe) As you move with more advanced process nodes and more chip complexity, which issues do you foresee/anticipate and how would you further refine this flow to address those new challenges?

Vincent: We’ve seen a steady increase in errors number with new processes adoption driven by the increasing complexity of chips. CustomSim perceived added value has consequently has steady upward trend. CustomSim CCK benefits from the more diverse and strict electrical overstress limits that come with smaller geometries.

New technologies enable convergence of applications on one IC: audio, connectivity and power management can be done on just one die in a process optimized for both high-voltage and logic density. This means more fast-Spice: a chip that has multiple and different use cases needs a complex power-supply architecture to optimize the power consumption on all cases. It therefore requires an extensive verification at transistor-level.

The technology is available to move along that path: we need to focus on verification quality and automation to keep coverage and schedule targets.

There is however an emerging trend that may require a disruption in technology: the nature of mixed signal design is changing. Mixed-signal previously meant Digital blocks in an Analog top or Analog blocks in a Digital top. What’s we are seeing now is designs with pervasive RTL in Analog and Digital blocks that instantiate tens of analog IPs. This calls for a fine-grain partitioning of analog and digital in mixed-signal verification, driven by signal path instead of block hierarchy.

Breaking the hierarchical partitioning barrier in mixed-signal verification means that a unified methodology could be used on all circuits, including SoC; it also enables the definition of a mixed-signal verification coverage metric.

Philippe: CustomSim  is really a comprehensive tool using all the expertise acquired for several generations of Fast- Spice simulators. Moving forward, it is crucial to maintain and keep refining the edge we have today for the following features:

  • ease of use by using a simple set of commands
  • speed by keeping  the runtime as low as possible even if  the SOA checks  are more and more complex
  • accuracy

Those features have shown to be a key differentiator , especially as we progress with STE toward more advanced process nodes.

Thanks Vincent and Philippe

For more information, you can see  STE technical papers at:

[1] Top-Down Electrical Verification of Mixed-Signal Power Management Circuits with HSIM CircuitCheck

[2] Top-Down Electrical Verification of Mixed-Signal Power Management Circuits with HSIM CircuitCheck

[3] Electrical Rule Check with XA at Chip Level to Detect Dynamic HiZ, Current Leakage and Overvoltage on Thin Oxides

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