Posted by Hélène Thibiéroz on June 26, 2012
A few months ago at 2012 San Jose SNUG, I attended the FinFET keynote speech by Professor Chenming Hu, the Father of FinFET. Professor Hu’s speech was exceptionally well received by the audience (more than 400 people). I had the opportunity to meet him . Because his keynote was really informative and because FinFET technology is an innovative and captivating subject, I asked Professor Hu to share more of his insights and vision on the FinFET technology with us.
Dr. Chenming Hu has been called the Father of 3D Transistors for leading FinFET development in 1999. Intel is the first company to use FinFET in 2011 production calling it the most radical shift in semiconductor technology in over 50 years. Other companies are expected to follow. IEEE called him “Microelectronics Visionary” and noted his pioneering contributions to integrated circuit reliability in presenting him the Nishizawa Medal for “achievements critical to producing smaller yet more reliable and higher-performance integrated circuits”. US Semiconductor Industry Association thanked him for research leadership for “advancement of the electronics industry and of our national economy”. IEEE EDS gave him the 2011 Education Award for “distinguished contributions to education and inspiration of students, practicing engineers and future educators”.
He has authored four books including a new textbook and 900 research papers, and has been granted over 100 US patents. He is a fellow of the IEEE and an Honorary Professor of CAS Microelectronics Institute and National Chiao Tung University. His many awards include the 2007 Andrew Grove Award for device reliability research and the 2002 Donald Pederson Award in Solid State Circuits for the BSIM standard transistor model. The 2009 SRC Aristotle Award recognized him as an influential mentor to many outstanding students. He has received UC Berkeley’s highest honor for teaching — the Berkeley Distinguished Teaching Award. He is researching green tunnel transistor for ultra-low-power electronics.
Dr. Hu received his B.S. degree from National Taiwan University, which honored him with the Distinguished Alumni Award in 2011, and the M.S. and Ph.D. degrees from UC Berkeley all in electrical engineering.
Q- Professor Hu, thank you very much for your excellent FinFET keynote speech at SNUG. It was historically well received (highest survey score among all SNUG events). We would like to thank you also as our guest speaker for Synopsys AMS blog. Can you elaborate on the most common challenges the industry has for the planar CMOS technology?
It was my pleasure to speak at SNUG. The basic planar CMOS transistor structure has not changed from the dawn of the IC era in the 1960’s. Since then, IC scaling has reduced the size or gate length of the transistor by a thousand times. This size scaling has given us tremendous benefits in cost, performance and power. Amazingly, the planar transistor has retained its desirable characteristics such as speed and leakage very well until the last decade.
In the last decade, the leakage power consumption increased more rapidly than before. Power supply voltage scaling had to slow down to accommodate higher threshold voltages and the result is rising chip power consumption. In addition, the leakage current became sensitive to the gate length variation. Heavy doping of the channel was employed to control the leakage but that led to Random Doping Fluctuation, causing random variations of the threshold voltage. Design for Manufacturing became necessary and added to the design cost.
Q- Why FinFET? How did you come up with this concept twelve years ago? Which issues does FinFET technology address and how?
In the 1980’s I researched the reliability and tunneling leakage of gate oxide. It was generally believed that the scaling limit of gate oxide thickness would determine the scaling limit of the channel length. The idea is that the gate voltage can control and turn off the leakage current regardless of the drain voltage if the gate is in much closer proximity to the leakage current path (along the oxide-silicon interface) than the drain.
That research made me realize that even an ideal gate oxide with nearly zero thickness would not allow the channel length to be scaled to nearly zero. This is because the quantum mechanical and electrostatic effects make the leakage current flow about ten nanometers below the oxide-silicon interface, not at the interface, if the channel length is about 20nm. So, making the oxide thickness nearly zero is not going to put the gate in closer proximity to the leakage current path than the drain. The solution, I reasoned, was to make sure that there is no silicon, no semiconductor, anywhere that is more than some nanometers away from the gate.
In the late 1990’s I led a team of researchers at University of California, Berkeley to demonstrat two new transistor structures that can be scaled to 10nm and beyond. We called one FinFET and the other UTB-SOI. Both have a thin silicon body in accordance to the no-silicon-far-from-gate concept. Both can have nearly ideal (63mV/decade) subthreshold swing and low sensitivities to gate length variation and random dopant fluctuation.
Q- What are the main advantages of FinFET over UTB (ultra-thin-body) SOI?
FinFET ‘s scaling path is clearer. 5nm FinFET has been demonstrated in industry fab and 3nm FinFET has been demonstrated in university lab. It is now the main stream CMOS technology. UTB-SOI is clearly superior to planar technology in performance/power and can be deployed as early as 28nm. However, its scaling limit is not as well understood.
Q- I now understand that FinFET has several strengths such as strong channel-control and low leakage control? What do you think using its application in SoC/analog designs?
FinFET is a superior analog transistor. For high-speed applications, a short channel would provide a higher speed to the analog circuits. Unfortunately, short channel transistors suffer from random dopant fluctuation and low output resistance, which degrade device matching and voltage gain. FinFET provides good analog characteristics and high speed and low power to the SOC/analog designs. Because FinFET does not require very aggressive high-k gate dielectric, the flicker noise can be better.
Q- Could you tell us more about the current FinFET status and challenges you envision and future R&D required for finer nodes?
Intel is the first company to adopt FinFET at 22nm. Major foundries have all announced plans to introduce FinFET at 14nm and there are discussions about whether the plan may be pulled in to 16nm or 18nm. Clearly new design tools are needed for FinFET’s discreteness of channel width, RC extraction etc. Much work is needed in manufacturing FinFET but that is what the fabs do so very well and I do not expect serious new challenges.
Q- Moving forward, for sub-10nm, what will be the major issues for the industry? Will the solution be FinFET?
FinFET and/or UTB-SOI structure will continue to serve the industry for many decades to come. However, additional innovations will be needed to address the power issue. We must reduce power consumption by an order of magnitude to make room for future growth in IC density and function. This will come from new transistor operation principles such as tunneling and ferroelectricity. Stay tuned.
You can access Professor Hu’s keynote speech at: