Posted by Hélène Thibiéroz on May 31, 2012
DAC is just around the corner and if you read my blog religiously (and I am sure you do :)), you should have seen a post a few days ago on our incoming DAC AMS lunch. During this event, five major companies (AMD, ARM, Global Foundries, Micron and NVIDIA) will talk about Verification using Synopsys portfolio of simulators. I wanted to give you “a taste” of this event by interviewing one of our speakers.
In this interview, Chad Lackey from AMD shares his insights about presenting at our DAC Synopsys AMS event the verification flow he successfully developed using CustomSim-VCS.
Chad Lackey is a Member of Technical Staff at Advanced Micro Devices. For the past 5 years, Chad has been a design engineer with the PCI-Express/HyperTransport SERDES team. Prior to joining AMD, Chad worked at Sandia National Laboratories as a Senior Member of Technical Staff focusing on analog integrated circuits and ASIC design. Chad holds a B.S.E.E. and M.S.E.E from New Mexico State University in Las Cruces, NM.
Q- Could you describe your job responsibilities at AMD ? What kind of circuits do you simulate using CustomSim-VCS and which specific simulator features/analyses do you focus on?
I am currently a design engineer with the PCI-Express and HyperTransport team at AMD. I’ve been responsible for several circuit designs within our PCIe and HyperTransport PHYs. One of my primary duties is to provide mixed-mode simulation support for our team. Using CustomSim-VCS, we focused most of our efforts on verifying the receiver-side analog macros and their digital control. These simulations include loops to verify offset cancellation, equalizer tuning, and clock-data-recovery loops. In addition to verifying the functional loops, we also utilized the power-analysis features of CustomSim to allow us to pinpoint high power sub blocks. By doing so, we can target both an effort to reduce the overall power of the macro along with meeting reliability challenges like electromigration.
Q- Why did you select CustomSim-VCS for AMS/Mixed-Signal Verification? Did you look at other vendors? What were the main compelling factors?
One big reason we selected CustomSim-VCS was setup time, as it was extremely easy in this case. We have looked at other vendors but found that the setup was much more time consuming. When you have 8 to 9 month design cycles, we need to be able to simulate the RTL and custom analog macros together at an early stage of the program. And, the second reason, which is critical, is speed. These loop simulations need microseconds of simulation time and the CustomSim-VCS tool gives us the ability to get a long simulation running and checked within the same day. Once satisfied with the first pass at lower accuracy levels, we can then selectively dial up that accuracy using a single command. This then gives the circuit designers confidence that we can match their SPICE results in a closed-loop simulation within a few percent of their open-loop estimates.
Q- Could you please describe at a high-level the paper you will be presenting at DAC next week ?
I will do my best to convey a couple of specific examples of how CustomSim-VCS enabled us to get quick turn-around on the interaction between RTL-based controllers and the SPICE custom analog circuitry.
Q- As you move below 28nm process nodes for AMD PCIe-Gen4, which issues do you foresee/anticipate?
The next big challenge for us will be data rate targets above 8Gbps like PCIe-Gen4 at 16Gbps. The specification is still in the process of being written and revised, but, in order to get a part to market, we have to look at these designs now. This means we need even more throughput from mixed-mode simulators so we can verify these designs. In addition, our hope is to use S-param based channel models to include in our mixed-mode efforts to fully test the design.
Thanks Chad !
For more information, you will be able to see Chad’s presentation at our DAC AMS lunch:
(1) This picture refers to the following paper published by AMD:
Extending HyperTransport™ Technology to 8.0 Gb/s in 32-nm SOI-CMOS Processors
Bruce A. Doyle1, Alvin L. S. Loke1, Sanjeev K. Maheshwari2, Charles L. Wang2, Dennis M. Fischette2,
Jeffrey G. Cooper1, Sanjeev K. Aggarwal2, Tin Tin Wee1, Chad O. Lackey1, Harishkumar S. Kedarnath3,
Michael M. Oshima2, Gerry R. Talbot4, and Emerson S. Fang2,
IEEE Asian Solid-State Circuits Conference, November 14-16, 2011, Jeju, Korea